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Question U7-based RISC-V SBC: $665

DrMrLordX

Lifer
Apr 27, 2000
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Looks like SiFive is going to sell a RISC-V SBC that has four U7 cores (the 4c U7 core complex is designated U74-MC). It's also got an S7 core in it, though I haven't yet figured out what that does. Article:


Price definitely isn't right. If you look at the U7 core:


Also please reference:


The U7 core leaves a lot to be desired. If I were going to buy a development platform to deploy software on other systems, I would want most (if not all) ISA extensions available, so I would have the ability to target nearly any present or future RISC-V system. With ARM I can get a Graviton2 instance and write ARM software that will run on any ARMv8 SoC out there - assuming it's running Linux. The U74-MC complex doesn't get you any SIMD/vector math, for example. ARM has had NEON for years.
 

Thala

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Nov 12, 2014
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The U7 core leaves a lot to be desired. If I were going to buy a development platform to deploy software on other systems, I would want most (if not all) ISA extensions available, so I would have the ability to target nearly any present or future RISC-V system.
You think too much of an application processor instead of an embedded development platform. These U7 cores do not even have an MMU, so forget about general application processor usage.
 

DrMrLordX

Lifer
Apr 27, 2000
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You think too much of an application processor instead of an embedded development platform. These U7 cores do not even have an MMU, so forget about general application processor usage.
It's being billed as an application processor though. Well partially anyway. There's a fair amount of hype surrounding RISC-V, such as:


Yeah if we just look at it as a dev platform for RISC-V embedded, then the board kind of makes sense. If we look at it to a precursor to serious competition for Intel and AMD, then it's a total fail.
 

Thala

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Nov 12, 2014
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It's being billed as an application processor though. Well partially anyway. There's a fair amount of hype surrounding RISC-V, such as:
Should tell you how big the mismatch between hype and reality is. On the SW side it is looking even worse, as you can imagine.
 

SarahKerrigan

Senior member
Oct 12, 2014
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You think too much of an application processor instead of an embedded development platform. These U7 cores do not even have an MMU, so forget about general application processor usage.
What are you talking about? Yes they do. All U-series cores have an MMU. S-series cores do not, AFAIK.
 

Thala

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Nov 12, 2014
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What are you talking about? Yes they do. All U-series cores have an MMU. S-series cores do not, AFAIK.
I should have been more specific. MMU in RISC-V is used for address translation only but not for protection and memory attributes. This means with these CPUs you cannot have any per-page protection. All current desktop OS assume you can set protection attributes per page. Also physical memory attributes are defined statically at design time and not on a per-page basis at runtime.
 
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SarahKerrigan

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Oct 12, 2014
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I should have been more specific. MMU in RISC-V is used for address translation only but not for protection and memory attributes. This means with these CPUs you cannot have any per-page protection. All current desktop OS assume you can set protection attributes per page. Also physical memory attributes are defined statically at design time and not on a per-page basis at runtime.
Not true. Page table entries for Sv39 (which is what the U74 uses) contain protection attributes like in every other mainstream MMU. PMP is just another protection layer on top of that, vaguely like MPUs in a lot of other embedded cores.

Personally I don't see the gain in having both, but it does. That doesn't mean its MMU can't do per-page protections, though.
 
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Thala

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Nov 12, 2014
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Not true. Page table entries for Sv39 (which is what the U74 uses) contain protection attributes like in every other mainstream MMU. PMP is just another protection layer on top of that, vaguely like MPUs in a lot of other embedded cores.

Personally I don't see the gain in having both, but it does. That doesn't mean its MMU can't do per-page protections, though.
I stand corrected. Seems only the memory type attributes are missing.
 

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