It is clear that TC can utilize PCI-E bandwidth accessing systemic memory for GPU use
But according to the article about 6200TC, there are several checkpoint for TC
1. How many bandwidths does the logic chip (in most case, Northbridge) provide?
2. The bandwidth between the logic chip and DIMM
Checkpoint No.1 of no doubt, can provide max 4GB/s up and 4GB/s down (Total 8GB/s) bandwidth for most of chipset, although several chips such as i915 only provide 3GB/s down and 1GB/s up.
My question is about 2.
The time when TC was out, there is no DRAM module can provide 8GB/s,
that's required Dual Channel DDR 500...so the problem comes
If we use Dual channel DDR 400, how many bandwidths can it provide for TC?
Still 8GB/s or down to 6.4GB/s?
If systemic DO influence the bandwidth of TC, the dual channel may play very important role in TC performance, because single channel DDR 400 can only provide 3.2GB/s while Dual channel DDR500 can provide 8GB/s bandwidth.
But according to the article about 6200TC, there are several checkpoint for TC
1. How many bandwidths does the logic chip (in most case, Northbridge) provide?
2. The bandwidth between the logic chip and DIMM
Checkpoint No.1 of no doubt, can provide max 4GB/s up and 4GB/s down (Total 8GB/s) bandwidth for most of chipset, although several chips such as i915 only provide 3GB/s down and 1GB/s up.
My question is about 2.
The time when TC was out, there is no DRAM module can provide 8GB/s,
that's required Dual Channel DDR 500...so the problem comes
If we use Dual channel DDR 400, how many bandwidths can it provide for TC?
Still 8GB/s or down to 6.4GB/s?
If systemic DO influence the bandwidth of TC, the dual channel may play very important role in TC performance, because single channel DDR 400 can only provide 3.2GB/s while Dual channel DDR500 can provide 8GB/s bandwidth.
