TSX borked in Haswell and Broadwell

[Phynaz]

Will be disabled via a microcode update.

http://techreport.com/news/26911/errata-prompts-intel-to-disable-tsx-in-haswell-early-broadwell-cpus

Nice going Intel, you screwed the pooch on this one.

 

[DrMrLordX]

This problem probably won't matter for desktop/mobile Haswell and Broadwell products. But, the real question is:

Does Haswell-E have this problem as well? If so, then that's quite a gaffe.

 

[exar333]

Boo. I was hoping TSX was going to start gaining some traction, now this.

 

[*NixUser]

Very unfortunate.

Sad for those who paid for a processor model that now has one less feature enabled (specially those who bought locked ones over unlocked models just for TSX).

 

[Fjodor2001]

Good thing I just read this. I was considering getting a 4670 instead of a 4670K for a new build, partly due to TSX not being enabled on the 4670K.

 

[TuxDave]

Well that sucks.

 

[SOFTengCOMPelec]

Did Intel know about this a year ago (very approximately), and hope nobody would notice ? (I hope not).

I remember the Pentium divide bug, but my Original Pentium with this bug I'm typing this message on, is not^*&£&%£^&£&%£%&£%*&%$&*$*hdfjhkejldhfehfwehwfheh56335734575474747hdhdhdhdhdhdhdhdhdh affecting anything I do, so I'm fine with it.

All jokes aside, this would completely put me off the upcoming Haswell-E/Haswel-EPs, until this thing is fixed (if they are affected).

 

[monstercameron]

there is a tiny bit of irony here but I guess everbody makes mistakes.

 

[Khato]

Pretty much a given that Intel didn't know about it else they would've had it fixed on Broadwell.

It is kinda sad that it's only being found over a year after release. Goes to show how much use those new instructions are getting eh?

 

[SOFTengCOMPelec]

Pretty much a given that Intel didn't know about it else they would've had it fixed on Broadwell.

It is kinda sad that it's only being found over a year after release. Goes to show how much use those new instructions are getting eh?

They really needed to enable/implement it on most/all of their current cpus, to help make it a success (as already said in this thread).

Good point about they would have removed it on broadwell.

It's also VERY embarrassing that Intel themselves failed to ever notice the bug in their testing/validation programme. They had a lot of stick over not noticing the original pentium divide bug, and said they would massively improve and never repeat the same mistake, with their testing/validation scheme (if I remember correctly).

 

[ShintaiDK]

That may explain the "wierd" Broadwell F stepping to come.

 

[SunnyD]

Usually something as major as this results in Intel silently allowing anybody that wants to to be allowed to trade in a retail purchased CPU with the errata for a new CPU revision that has the errata corrected if available. Often times this also will apply to OEM's as well (directly via the OEM though).

 

[Nothingness]

It is kinda sad that it's only being found over a year after release. Goes to show how much use those new instructions are getting eh?

Why would devs spend time on instructions which are fused off on the vast majority of CPU sold by Intel?

 

[SPBHM]

Usually something as major as this results in Intel silently allowing anybody that wants to to be allowed to trade in a retail purchased CPU with the errata for a new CPU revision that has the errata corrected if available. Often times this also will apply to OEM's as well (directly via the OEM though).

it's only fair, the CPU have advertised a feature that does not work properly and is now going to be disabled...
if you feel affected by it you should be able to do something about it,


in reality it's not going to change anything for most users (the time it took for someone to find the problem is very telling), but who knows, if in a few years TSX could be relevant and you can't use it because of this with the old CPUs...

 

[SPBHM]

Why would devs spend time on instructions which are fused off on the vast majority of CPU sold by Intel?

4790K/4690K have it enabled, same as all the locked i5s/i7s 4570+

 

[SOFTengCOMPelec]

Why would devs spend time on instructions which are fused off on the vast majority of CPU sold by Intel?

Searching round the web about this, some people reckon that TSX is important to the soon to be released Haswel-E/Haswell-EPs, because with lots of cores, and a server which has database software (or whatever they are doing with it) updated to use TSX, they will be rather disappointed. The Wiki about the TSX instruction reckons that TSX makes a huge speed difference, with lots of cores and big databases.
I still have not been able to confirm one way or other, if Haswel-E/Haswell-EPs are affected, but they could well be. But not definitely, because they have an improved or at least bigger cache (I think), which might mean the bug is not present, as TSX has a lot to do with caches, I believe.

Source

According to benchmarks, TSX can provide around 40% faster applications execution in specific workloads, and 4–5 times more database transactions per second (TPS).

So it sounds like a potentially big deal for servers, depending on how much TSX was going to be implemented, on servers.

 

[Nothingness]

4790K/4690K have it enabled, same as all the locked i5s/i7s 4570+

I don't think these represent the vast majority of CPU sold by Intel

 

[ShintaiDK]

Searching round the web about this, some people reckon that TSX is important to the soon to be released Haswel-E/Haswell-EPs, because with lots of cores, and a server which has database software (or whatever they are doing with it) updated to use TSX, they will be rather disappointed. The Wiki about the TSX instruction reckons that TSX makes a huge speed difference, with lots of cores and big databases.
I still have not been able to confirm one way or other, if Haswel-E/Haswell-EPs are affected, but they could well be. But not definitely, because they have an improved or at least bigger cache (I think), which might mean the bug is not present, as TSX has a lot to do with caches, I believe.

It requires software to use it. And there is no commercial software that uses it. By the time it may get here, I bet you those Haswell-EPs have been replaced due to TCO.

The only impact as such to this is slower TSX development by 1-2 years. Not that it was around the corner to begin with.

 

[SOFTengCOMPelec]

It requires software to use it. And there is no commercial software that uses it. By the time it may get here, I bet you those Haswell-EPs have been replaced due to TCO.

The only impact as such to this is slower TSX development by 1-2 years. Not that it was around the corner to begin with.

I agree.
The fact that it has taken over a year (I think), for someone to even notice this problem/bug, tends to show how little TSX has been used so far.

Just don't drive under any bridges, anywhere in the world, until this thing is fixed (Joke).

 

[cytg111]

What an elaborate fubar. One of the defining features between K and non-K models ... that whole scheme and segmentation just hit the floor hard. I expect that very same microcode to unlock my 4770 thank you. (yea right, like that is happening).

 

[TerryMathews]

Will Intel be refunding the cost of that TSX instruction to affected purchasers?

 

[cytg111]

Why would devs spend time on instructions which are fused off on the vast majority of CPU sold by Intel?

Why would they not optimize for performance? Stay ahead of the curve? Why no settle for being second best in their field? Or third? .. Many questions.. even more answers.

 

[Redstorm]

Haswell-ep and e's are affected by this and will be disabled in microcode..

I wonder if Intel will replace free of charge Haswell-e's affected by this bug when new silicone arrives..

 

[Khato]

Why would devs spend time on instructions which are fused off on the vast majority of CPU sold by Intel?

Because they should simply be using a library or wrapper for applicable multi-threaded sync functions/shared data applications such that non-compatible CPUs use the legacy path while those supporting TSX can take advantage of it? (Note that this is with respect to the HLE portion - RTM doesn't play as nicely with backwards compatibility.) Which I guess it might be the case that the bug is on the RTM side, since that's more likely to only start being used in software with the ramp up towards HSW server parts... and even if there's only a bug in one but not the other they'd have to disable the entire feature.

 

[Magic Carpet]

What an elaborate fubar. One of the defining features between K and non-K models ... that whole scheme and segmentation just hit the floor hard. I expect that very same microcode to unlock my 4770 thank you. (yea right, like that is happening).

Yeah, looks like my 4770K wasn't such a bad buy after all, lol.