TSMC announces 6 nm node

[jpiniero]

https://www.tsmc.com/uploadfile/pr/newspdf/THWQWQTHTH/NEWS_FILE_EN.pdf

Says risk production in 1Q 2020 with 18% density improvement over 7 nm EUV. Seems to be mainly a upgrade path for companies with 7 nm products who don't want to pay 5 nm's design costs.

Could be an option for AMD for some products.

 

[exquisitechar]

https://www.tsmc.com/uploadfile/pr/newspdf/THWQWQTHTH/NEWS_FILE_EN.pdf

Says risk production in 1Q 2020 with 18% density improvement over 7 nm EUV. Seems to be mainly a upgrade path for companies with 7 nm products who don't want to pay 5 nm's design costs.

7nm DUV, not EUV.

EUV 7nm+ is supposed to be about that much denser than 7nm DUV as well. What's the difference between 7nm+ and 6nm?

 

[jpiniero]

EUV 7nm+ is supposed to be about that much denser than 7nm DUV as well. What's the difference between 7nm+ and 6nm?

Hmm, that's a good question. I am assuming they mean 18% better density compared to 7 EUV, might be a typo.

 

[JasonLD]

Hmm, that's a good question. I am assuming they mean 18% better density compared to 7 EUV, might be a typo.

Or just a fancier way to call slightly more refined 7nm EUV.

 

[krumme]

Perhaps it's just because Intel 7nm is shaping up good so they need a new name or their own 5nm is delayed and this is made to draw attention away

 

[jpiniero]

Perhaps it's just because Intel 7nm is shaping up good so they need a new name or their own 5nm is delayed and this is made to draw attention away

Actually it was Samsung saying that their 7 nm EUV node is now in HVM, and they also have a "5 nm" node that is now in risk production; and at least according to WikiChip is analogous to TSMC's 6 nm in terms of the idea that it's an upgrade option for existing 7 nm designs.

 

[NostaSeronx]

Samsung also has a 6nm node, which has a single tapeout;
"Also, Samsung is collaborating with customers on 6nm, a customized EUV-based process node, and has already received the product tape-out of its first 6nm chip."
https://news.samsung.com/global/sam...ter-area-scaling-and-ultra-low-power-benefits

 

[turtile]

https://www.tsmc.com/uploadfile/pr/newspdf/THWQWQTHTH/NEWS_FILE_EN.pdf

Says risk production in 1Q 2020 with 18% density improvement over 7 nm EUV. Seems to be mainly a upgrade path for companies with 7 nm products who don't want to pay 5 nm's design costs.

Could be an option for AMD for some products.

Seems like a perfect shrink for consoles built on 7nm without a lot of cost involved.

 

[name99]

7nm DUV, not EUV.

EUV 7nm+ is supposed to be about that much denser than 7nm DUV as well. What's the difference between 7nm+ and 6nm?

Remember Intel claimed (and, of course did not deliver...) that 10nm would be improved over 14nm through not just lithography but hyperscaling boosters like Contact Over Gate, and Single rather than Double Diffusion break. These are technical details regarding how close transistors are to each other, or whether space has to be provided or not for contact with the metal layer above.
What appears to be happening (we know this with SS, it's probably the same with TSMC) is that they are slowly introducing these same scaling boosters into their processes, but one at a time in a controlled fashion, not all at once (in a non-debuggable disaster). So SS 5nm appears to be (I think I have this right) their previous 7nm design rules with a few improvements but the main density tweak being a switch from DDB to SDB.

So, as far as I can tell, what we have with TSMC is
7nm
7nm+ = 7nm with a few layers done as EUV
6nm = 7nm with something like SDB rather than DDB.

So why do this? Well, it boosts your 7nm density slightly WITHOUT requiring EUV, and EUV machines are currently in short supply.
Why introduce 7nm+?
(a) I'm guessing they weren't sure that they could SDB to work, so didn't want to promise the 6nm boost at the time 7nm+ was introduced
(b) 7nm+ was a good learning experience on the way the 5nm AND will probably be of value to customers at some point once EUV machines are more plentiful.

The larger point is that you HAVE TO REMEMBER that TSMC (and SS) are not in the business of selling "leading edge process and nothing else"! They are in the business of selling "whatever your performance/price tradeoffs, we have something for you". That includes not just keeping older nodes alive, it ALSO includes providing a constant stream of improvements to those old nodes to make it easier for non-top-tier customers to improve their products without having to leap to a whole new node.

The second point you have to remember is that all of this is WHY TSMC and SS advance every year without drama --- because instead of trying to make ten changes at once in a huge leap to a new node, each small improvement is prototyped just by itself, simultaneously delivering some value to some customer, and providing a secure foundation on which to test the next improvement.

 

[moinmoin]

The second point you have to remember is that all of this is WHY TSMC and SS advance every year without drama --- because instead of trying to make ten changes at once in a huge leap to a new node, each small improvement is prototyped just by itself, simultaneously delivering some value to some customer, and providing a secure foundation on which to test the next improvement.

Should be noted that this is also an advantage of pure play foundries. Intel not being one likely always kept in mind the subsequent cost of adapting die designs to the new node, so for them combining as much new tech into a new node as possible was financially preferable (and almost necessarily led to the current 10nm disaster). Pure play foundries can ignore it, and their customers can pick the preferred nodes without having to pay for the in-between step nodes they don't actually use.