Knupt,
The 430tx limit was the CACHEABLE limit, NOT the physical memory limit. These chipsets had tag RAM in them that mapped the data in the cache to the physical memory address it matches up with. On this chipset, it only had enough tag RAM to address up to 64Meg of system RAM. This did not limit the amount of RAM you could use though. What happened is if you had more memory than it could tag, then all the memory above that limit would not be cached at all. The CPU could still use, but it wasn't cached, so it was slower than the memory that was cached. Of course, this little limitation was made all the more worse by Windows: it starts with the high memory addresses and works down. So, instead of having that extra bit of memory when you needed (which is still many times faster than a hard drive), Windows starts out in the uncached, slow memory region. The more memory you added, the more uncached memory you had to go through before it started to use the cache. Isn't that a nice set of limitations? That kind of reminds me of the IDE/DOS/BIOS set of limitations that put the original constaraints on the FAT file system.
The tag RAM issue pretty much went out the window with the PII and up processors. They had the cache on the same card as the CPU and the cache controller that was included could tag up to 512Megs (and remember, this was at a time when 64Megs was a LOT of memory). The newer PIIs and all PIIIs can cache 2 or 4 Gigs or RAM. And 4 Gigs is the hardware limit for a 32 bit memory address bus, so that should work OK until we move to 64 bit systems.