True capacity for a DIMM Slot

[Kamui]

Ok,

I got this stupid question. I was reading my bp6 motherboard specs and it stated that the Max Ram stick that each memory slot can take is 256mb. Have anyone tried putting a stick of 512 per say? Is it really a limitation of the motherboard or is it just marketing?

thanks

Kamui

 

[Keego]

I've only tried 256 in both of the ones I've had

 

[Rand]

With the BP6 it's a partial limitation of the chipset in combination with the actual motherboard design. I have seen 512MB modules work in a BP6 but it seems to be very touchy, and picky about which modules it will operate properly with. I'd suggest you stick with 256MB and smaller DIMM"s in a BP6.

 

[knutp]

I have an old chaintech motherboard, with 430tx chipset. The chipset doesn't take more than 64 mb ram cachable. I had one 64 mb, and it worked great for the 3 years till it didn't like to work anymore. And the manual states that the motherboard supports 64 mb dimms, but hadn't been testet before they made the manual.

But when the ram went bad I had to use another stick. And the only one I had was a 128 mb apacer pc133. And it worked great. Although I got another 64 mb since it workes just as fast with 64 than 128 (if not faster in normal programs). So the moral here is that that particular motherboard could use more memory than it was stated. But then again there are some motherboard that surely doesn't work with larger dimms than stated in the manual.

 

[AndyHui]

It's a chipset problem. The BX chipset supports up to 128mbit for chip densities per RAS line (sides of RAM), meaning that the largest DIMM each slot can support is a 256MB double sided DIMM (at 8 chips of RAM per side). The only way you can get a 512MB DIMM in there is to have a "double decker" style DIMM which has 16 chips on each side.

Certain very late steppings of the BX chipset may be able to handle 512MB DIMMs, but don't count on the BP6 having them.

 

[Snooper]

Knupt,

The 430tx limit was the CACHEABLE limit, NOT the physical memory limit. These chipsets had tag RAM in them that mapped the data in the cache to the physical memory address it matches up with. On this chipset, it only had enough tag RAM to address up to 64Meg of system RAM. This did not limit the amount of RAM you could use though. What happened is if you had more memory than it could tag, then all the memory above that limit would not be cached at all. The CPU could still use, but it wasn't cached, so it was slower than the memory that was cached. Of course, this little limitation was made all the more worse by Windows: it starts with the high memory addresses and works down. So, instead of having that extra bit of memory when you needed (which is still many times faster than a hard drive), Windows starts out in the uncached, slow memory region. The more memory you added, the more uncached memory you had to go through before it started to use the cache. Isn't that a nice set of limitations? That kind of reminds me of the IDE/DOS/BIOS set of limitations that put the original constaraints on the FAT file system.

The tag RAM issue pretty much went out the window with the PII and up processors. They had the cache on the same card as the CPU and the cache controller that was included could tag up to 512Megs (and remember, this was at a time when 64Megs was a LOT of memory). The newer PIIs and all PIIIs can cache 2 or 4 Gigs or RAM. And 4 Gigs is the hardware limit for a 32 bit memory address bus, so that should work OK until we move to 64 bit systems.

 

[AndyHui]

Tag RAM was not needed once the L2 cache migrated to the processor, ie the Pentium Pro. The PPro can cache 4GB of RAM, the Klamath Pentium II 512MB, but the Deschutes Pentium II and Katmai Pentium III can cache 4GB.

The Coppermine and Tualatin processors can cache up to 64GB of RAM.