Transistors and Gates

[ClassicCCF]

http://en.wikipedia.org/wiki/I...cement-type_MOSFET.JPG
http://en.wikipedia.org/wiki/Image:N-channel_mosfet.JPG

I have this diagram of a transistor... it shows the source of negetive particles flowing from the sysem clock through an illuminum lead that penetrates through a layer of silicon dioxide to connect to a layer of N-type silicon. The drain is exactly identical except it is divided from the source lead under a layer of positively charged polysilicon which is burried in the layer of silicon dioxide that the source and drain are penetrating through. There is a lower layer of P-type silicon which contains the two divided segments of N-type silicon and is shown to have a vacuum for negative particles when the polysilicon is given a positive charge because the positively charged polysilicon pulls electrons from the P-type silicon.

From what I understand it works like turning on a light switch, the action of flipping the switch on is the same as adding the positive charge to the polysilicon. What I don't understand is how this infuences a logic gate such as a not gate (which has one transistor), my question is with a not gate, is the added 0 or 1 coming through the source or through the polysilicon connection? and... what connection on the transistor is this recorded through to receive the oposite binary digit? When I look at my diagram of a not gate, the clock pulse is stopped by the circuit being oppened when a 1 is added as the input bit and this causes the output to be 0. When the input bit is 0 the circuit is closed and the output bit is 1. I understand the logic of the gate, but I am wondering if the clock pulse is equivelant to the source lead, the input bit is equivelant to the polysilicon positive charge, and the output bit is equivelant to the drain lead. hopefully this all makes sense.

 

[ClassicCCF]

I have found an indepth explanation of the definitions of electron flow through the transistor. All I need to know now is how the transitor components directly apply to a NOT Gate.

http://www.privateline.com/transistor/index.html

 

[PottedMeat]

... your terminology is confusing. You should try understanding in general how a MOSFET element works first then look at the device physics.

http://en.wikipedia.org/wiki/Image:NMOS_NOT.png

For a NMOSFET NOT gate you attach a resistor between V+ and the drain. You ground the source terminal. Take input voltage readings at the gate terminal, take output voltage readings at the junction of the resistor and the drain. When you apply a low voltage to the gate, no current flows ( assume a high resistance between the source and drain ) between the drain and source so the output terminal is at V+. When you apply a high voltage to the gate, current flows between the drain and source ( assume no resistance between drain and source at this point ) and the output terminal is at ground. So a high input gives a low output and a low input gives a high output. Of course this is vastly simplified but thats the basic operation.

 

[ClassicCCF]

I apologize if my terminology is lacking in any way. I appreciate your response and I hope this will be readable. From what I understand you are saying that the lead out (or drain) is not where a reading is taken to determine the output, but that it is located where the drain meets the resistor (or the N-type silicon)? Can you explain the process by which this output is passed to another transistor in a logic gate?

 

[CTho9305]

What is your background?

When I look at my diagram of a not gate, the clock pulse is stopped by the circuit being oppened when a 1 is added as the input bit and this causes the output to be 0.

What are you looking at that has a clock signal?

From what I understand you are saying that the lead out (or drain) is not where a reading is taken to determine the output, but that it is located where the drain meets the resistor (or the N-type silicon)?

I don't understand the distinction you're seeing here. If two points are wired together, they're treated as the same node unless you're doing analysis so detailed that wires become significant.

Can you explain the process by which this output is passed to another transistor in a logic gate?

There is no "process" - the output node of one logic gate is connected to some of the polysilicon gates in the next logic gates. As the first gate evaluates, its output voltage changes, which then causes the second gate's transistors to switch. For BJTs, the circuit is controlled with currents rather than voltages, but you should really worry about only one of the transistor types when you're just learning.

 

[degibson]

Look at this at a slightly higher level:
NMOS Inverter
CMOS Inverter

 

[ClassicCCF]

I'm obviously missing something... I will do some more studying and repost a different topic on a later date. Thank you to all those who have posted to this topic.

 

[TuxDave]

Hmmm I thought you got your answer. I hope you come back to look at this response.

Let's start by summarizing what you do know:
1) Transistors act like switches and the gate controls whether the drain and source are connected or if they are disconnected.

You need to also know what you have to do to the gate to control the switch. There are two types of transistors (NMOS and PMOS) that act in opposite ways. One you add charge to the gate to close the switch (NMOS) and the other you add charge to open the switch(PMOS).

Given that, how does a NOT gate work? In a general case, you need both PMOS and NMOS transistors to make a NOT gate. The NMOS will connect between a "0" and the output and the PMOS will connect between a "1" and the output. The input is actually attached to BOTH gates.

So to walk through this, when you add charge to both gates, the NMOS source/drain is connected and the PMOS is disconnected making the output connect to the "0" and so the output is "0" when the input is "1" (1 being the addition of charge).

The opposite happens when you remove charge, the NMOS's source/drain is disconnected and PMOS is connected making the output connect to the "1". So an input of "0" (removing the charge from the gate) results in an output of "1". Hence the not gate in action.

As for the whole "source" vs "drain" part, you did correctly note that most of the time they are symmetrical. It turns out that source and drain is named arbitrarily depending on how they are hooked up to a circuit. The NMOS's naming convention always has the source attached to the lowest value and the drain attached to the higher value of charge. So in my example above when the NMOS connects 0 and the output, the 0 is connected to the source and the output is connected to the drain. So in the case where the NOT gate is outputting a "0" THROUGH the NMOS, you are measuring the value on the DRAIN.

The PMOS is the opposite where the higher value is attached to the source, etc...

 

[Smilin]

My favorite book:
http://www.amazon.com/Code-Dv-...&qid=1219257795&sr=8-1