Transistor gate length

[rimshaker]

When the industry talks about 0.18u and 0.13u processes, they're talking about the gate length (channel length) of a typical MOS transistor. However, there are 3 ways to measure gate length: 1) from the photo mask, 2) actual length between source and drain edges, and 3) the effective gate length which takes into account encroachment and LDD features underneath the gate. So which one does Intel and AMD refer to when they talk about it?

 

[StandardCell]

<< When the industry talks about 0.18u and 0.13u processes, they're talking about the gate length (channel length) of a typical MOS transistor. However, there are 3 ways to measure gate length: 1) from the photo mask, 2) actual length between source and drain edges, and 3) the effective gate length which takes into account encroachment and LDD features underneath the gate. So which one does Intel and AMD refer to when they talk about it? >>



Most IC houses rate them on the actual drawn length. The photo masks have some weird phase correction shapes so you really can't determine gate length from just looking at it, but basically it's the size of the pattern of light that hits the polysilicon (gate material). Of course, the effective length is going to be smaller after processing. Some places, like LSI Logic, like to get creative and quote 0.13um effective and THEN in brackets 0.18um drawn, or some such. But basically, the Intel and AMD quoted numbers are what they are drawn at in the GDS2 artwork and what eventually gets projected onto the photoresist when drawing out the polysilicon gate, and not what it actually looks like if you cross-section the processed wafer and look at it under the microscope. To quote anything else is pretty transparent (pardon the pun) to anyone with even a basic technical understanding of the industry. Also, it's not as meaningful when you look at other factors, like SRAM density, power dissipation, speed, dielectric reliability, intellectual property availability and a few other factors.