- Jun 30, 2004
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At least a couple times in the most recent two or three pages of "CPUs and Overclocking" threads, I and others have referenced and linked an article from Anandtech in 2007 on "Overclocking the QX9650: . . . The rules have changed" or something to that effect.
To repeat the essential synopsis, there is a voltage spike that occurs during the transition from extreme load to idle for our Intel processors. the spike would not be detectable or measureable without special equipment. It's maximum amplitude would vary inversely with the load severity and vDroop, so the largest vDroop and lowest load VCORE would generate a spike of the maximum amplitude, while less or partially-loaded transitions to idle would generate a spike of lesser magnitude. How you use your computer would affect the average size of the spike; year-long 24/7 Folding@Home might have the highest average spike/amplitude, but fewer of them. A mixture of office, gaming and media software might have the lowest average spikes, but likely more than the severely-loaded example.
Introduce the factor of load-line calibration or LLC. As I read that [now old and archival] article, increasing levels of LLC push upward the lowest VCORE and narrow the range to idle, while pushing the transition spike above the equilibrium idle or "turbo-idle" level, and and possibly above the maximum VID as set in BIOS.
I just today have come across some forum discussions touting recent-generation motherboard features to diminish the potential importance of these spikes, or at least an "accounting" of them as we choose our target speed, voltage and other BIOS factors.
Specifically, some of our motherboards -- including my [sooo last-gen] P8Z68 board -- have "overvoltage" protections which would seem to address these issues in configuring VCORE, Offset, Turbo-Voltage or "Extra V.. . . for Turbo-Mode," and the LLC setting.
Is this a reliable assumption? Do some chipsets and hardware reduce the uncertainties or their severity posed in the 2007 Anandtech article?
To repeat the essential synopsis, there is a voltage spike that occurs during the transition from extreme load to idle for our Intel processors. the spike would not be detectable or measureable without special equipment. It's maximum amplitude would vary inversely with the load severity and vDroop, so the largest vDroop and lowest load VCORE would generate a spike of the maximum amplitude, while less or partially-loaded transitions to idle would generate a spike of lesser magnitude. How you use your computer would affect the average size of the spike; year-long 24/7 Folding@Home might have the highest average spike/amplitude, but fewer of them. A mixture of office, gaming and media software might have the lowest average spikes, but likely more than the severely-loaded example.
Introduce the factor of load-line calibration or LLC. As I read that [now old and archival] article, increasing levels of LLC push upward the lowest VCORE and narrow the range to idle, while pushing the transition spike above the equilibrium idle or "turbo-idle" level, and and possibly above the maximum VID as set in BIOS.
I just today have come across some forum discussions touting recent-generation motherboard features to diminish the potential importance of these spikes, or at least an "accounting" of them as we choose our target speed, voltage and other BIOS factors.
Specifically, some of our motherboards -- including my [sooo last-gen] P8Z68 board -- have "overvoltage" protections which would seem to address these issues in configuring VCORE, Offset, Turbo-Voltage or "Extra V.. . . for Turbo-Mode," and the LLC setting.
Is this a reliable assumption? Do some chipsets and hardware reduce the uncertainties or their severity posed in the 2007 Anandtech article?
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