Info TOP 20 of the World's Most Powerful CPU Cores - IPC/PPC comparison

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Richie Rich

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Added cores:
  • A53 - little core used in some low-end smartphones in 8-core config (Snapdragon 450)
  • A55 - used as little core in every modern Android SoC
  • A72 - "high" end Cortex core used in Snapdragon 625 or Raspberry Pi 4
  • A73 - "high" end Cortex core
  • A75 - "high" end Cortex core
  • Bulldozer - infamous AMD core
Geekbench 5.1 PPC chart 6/23/2020:

Pos
Man
CPU
Core
Year
ISA
GB5 Score
GHz
PPC (score/GHz)
Relative to 9900K
Relative to Zen3
1​
Nuvia​
(Est.)​
Phoenix (Est.)​
2021​
ARMv9.0​
2001​
3.00​
667.00​
241.0%​
194.1%​
2​
Apple​
A15 (est.)​
(Est.)​
2021​
ARMv9.0​
1925​
3.00​
641.70​
231.8%​
186.8%​
3​
Apple​
A14 (est.)​
Firestorm​
2020​
ARMv8.6​
1562​
2.80​
558.00​
201.6%​
162.4%​
4​
Apple​
A13​
Lightning​
2019​
ARMv8.4​
1332​
2.65​
502.64​
181.6%​
146.3%​
5​
Apple​
A12​
Vortex​
2018​
ARMv8.3​
1116​
2.53​
441.11​
159.4%​
128.4%​
6​
ARM Cortex​
V1 (est.)​
Zeus​
2020​
ARMv8.6​
1287​
3.00​
428.87​
154.9%​
124.8%​
7​
ARM Cortex​
N2 (est.)​
Perseus​
2021​
ARMv9.0​
1201​
3.00​
400.28​
144.6%​
116.5%​
8​
Apple​
A11​
Monsoon​
2017​
ARMv8.2​
933​
2.39​
390.38​
141.0%​
113.6%​
9​
Intel​
(Est.)​
Golden Cove (Est.)​
2021​
x86-64​
1780​
4.60​
386.98​
139.8%​
112.6%​
10​
ARM Cortex​
X1​
Hera​
2020​
ARMv8.2​
1115​
3.00​
371.69​
134.3%​
108.2%​
11
AMD
5900X (Est.)
Zen 3 (Est.)
2020
x86-64
1683
4.90
343.57
124.1%
100.0%
12​
Apple​
A10​
Hurricane​
2016​
ARMv8.1​
770​
2.34​
329.06​
118.9%​
95.8%​
13​
Intel​
1065G7​
Icelake​
2019​
x86-64​
1252​
3.90​
321.03​
116.0%​
93.4%​
14​
ARM Cortex​
A78​
Hercules​
2020​
ARMv8.2​
918​
3.00​
305.93​
110.5%​
89.0%​
15​
Apple​
A9​
Twister​
2015​
ARMv8.0​
564​
1.85​
304.86​
110.1%​
88.7%​
16
AMD
3950X
Zen 2
2019
x86-64
1317
4.60
286.30
103.4%
83.3%
17​
ARM Cortex​
A77​
Deimos​
2019​
ARMv8.2​
812​
2.84​
285.92​
103.3%​
83.2%​
18​
Intel​
9900K​
Coffee LakeR​
2018​
x86-64​
1384​
5.00​
276.80​
100.0%​
80.6%​
19​
Intel​
10900K​
Comet Lake​
2020​
x86-64​
1465​
5.30​
276.42​
99.9%​
80.5%​
20​
Intel​
6700K​
Skylake​
2015​
x86-64​
1032​
4.00​
258.00​
93.2%​
75.1%​
21​
ARM Cortex​
A76​
Enyo​
2018​
ARMv8.2​
720​
2.84​
253.52​
91.6%​
73.8%​
22​
Intel​
4770K​
Haswell​
2013​
x86-64​
966​
3.90​
247.69​
89.5%​
72.1%​
23​
AMD​
1800X​
Zen 1​
2017​
x86-64​
935​
3.90​
239.74​
86.6%​
69.8%​
24​
Apple​
A13​
Thunder​
2019​
ARMv8.4​
400​
1.73​
231.25​
83.5%​
67.3%​
25​
Apple​
A8​
Typhoon​
2014​
ARMv8.0​
323​
1.40​
230.71​
83.4%​
67.2%​
26​
Intel​
3770K​
Ivy Bridge​
2012​
x86-64​
764​
3.50​
218.29​
78.9%​
63.5%​
27​
Apple​
A7​
Cyclone​
2013​
ARMv8.0​
270​
1.30​
207.69​
75.0%​
60.5%​
28​
Intel​
2700K​
Sandy Bridge​
2011​
x86-64​
723​
3.50​
206.57​
74.6%​
60.1%​
29​
ARM Cortex​
A75​
Prometheus​
2017​
ARMv8.2​
505​
2.80​
180.36​
65.2%​
52.5%​
30​
ARM Cortex​
A73​
Artemis​
2016​
ARMv8.0​
380​
2.45​
155.10​
56.0%​
45.1%​
31​
ARM Cortex​
A72​
Maya​
2015​
ARMv8.0​
259​
1.80​
143.89​
52.0%​
41.9%​
32​
Intel​
E6600​
Core2​
2006​
x86-64​
338​
2.40​
140.83​
50.9%​
41.0%​
33​
AMD​
FX-8350​
BD​
2011​
x86-64​
566​
4.20​
134.76​
48.7%​
39.2%​
34​
AMD​
Phenom 965 BE​
K10.5​
2006​
x86-64​
496​
3.70​
134.05​
48.4%​
39.0%​
35​
ARM Cortex​
A57 (est.)​
Atlas​
0​
ARMv8.0​
222​
1.80​
123.33​
44.6%​
35.9%​
36​
ARM Cortex​
A15 (est.)​
Eagle​
0​
ARMv7 32-bit​
188​
1.80​
104.65​
37.8%​
30.5%​
37​
AMD​
Athlon 64 X2 3800+​
K8​
2005​
x86-64​
207​
2.00​
103.50​
37.4%​
30.1%​
38​
ARM Cortex​
A17 (est.)​
0​
ARMv7 32-bit​
182​
1.80​
100.91​
36.5%​
29.4%​
39​
ARM Cortex​
A55​
Ananke​
2017​
ARMv8.2​
155​
1.60​
96.88​
35.0%​
28.2%​
40​
ARM Cortex​
A53​
Apollo​
2012​
ARMv8.0​
148​
1.80​
82.22​
29.7%​
23.9%​
41​
Intel​
Pentium D​
P4​
2005​
x86-64​
228​
3.40​
67.06​
24.2%​
19.5%​
42​
ARM Cortex​
A7 (est.)​
Kingfisher​
0​
ARMv7 32-bit​
101​
1.80​
56.06​
20.3%​
16.3%​

GB5-PPC-evolution.png

GB5-STperf-evolution.png

TOP10PPC_CPU_frequency_evolution_graph.png



TOP 10 - Performance Per Area comparison at ISO-clock (PPA/GHz)

Copied from locked thread. They try to avoid people to see this comparison how x86 is so bad.[/B]

Pos
Man
CPU
Core
Core Area mm2
Year
ISA
SPEC PPA/Ghz
Relative
1​
ARM Cortex​
A78​
Hercules​
1.33​
2020​
ARMv8​
9.41​
100.0%​
2​
ARM Cortex​
A77​
Deimos​
1.40​
2019​
ARMv8​
8.36​
88.8%​
3​
ARM Cortex​
A76​
Enyo​
1.20​
2018​
ARMv8​
7.82​
83.1%​
4​
ARM Cortex​
X1​
Hera​
2.11​
2020​
ARMv8​
7.24​
76.9%​
5​
Apple​
A12​
Vortex​
4.03​
2018​
ARMv8​
4.44​
47.2%​
6​
Apple​
A13​
Lightning​
4.53​
2019​
ARMv8​
4.40​
46.7%​
7​
AMD​
3950X​
Zen 2​
3.60​
2019​
x86-64​
3.02​
32.1%​



It's impressive how fast are evolving the generic Cortex cores:
  • A72 (2015) which can be found in most SBC has 1/3 of IPC of new Cortex X1 - They trippled IPC in just 5 years.
  • A73 and A75 (2017) which is inside majority of Android smart phones today has 1/2 IPC of new Cortex X1 - They doubled IPC in 3 years.

Comparison how x86 vs. Cortex cores:
  • A75 (2017) compared to Zen1 (2017) is loosing massive -34% PPC to x86. As expected.
  • A77 (2019) compared to Zen2 (2018) closed the gap and is equal in PPC. Surprising. Cortex cores caught x86 cores.
  • X1 (2020) is another +30% IPC over A77. Zen3 need to bring 30% IPC jump to stay on par with X1.

Comparison to Apple cores:
  • AMD's Zen2 core is slower than Apple's A9 from 2015.... so AMD is 4 years behind Apple
  • Intel's Sunny Cove core in Ice Lake is slower than Apple's A10 from 2016... so Intel is 3 years behind Apple
  • Cortex A77 core is slower than Apple's A9 from 2015.... but
  • New Cortex X1 core is slower than Apple's A11 from 2017 so ARM LLC is 3 years behind Apple and getting closer



GeekBench5.1 comparison from 6/22/2020:
  • added Cortex X1 and A78 performance projections from Andrei here
  • 2020 awaiting new Apple A14 Firestorm core and Zen3 core
Updated:



EDIT:
Please note to stop endless discussion about PPC frequency scaling: To have fair and clean comparison I will use only the top (high clocked) version from each core as representation for top performance.
 
Last edited:
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Gideon

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Geekbench does not scale linearly with clock speed so it will be a bit less (this is anothher reason why this graph is inheritly unfair, a 4Ghz A14 would have noticable worse score)

But yeah, if A14 can go anywhere near 4 Ghz it will be tha fastest CPU by quite a margin
 
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Hitman928

Diamond Member
Apr 15, 2012
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So you claim that Epyc has 321.7 pts/GHz => higher IPC than Ice Lake. Show me at least 3 good reviews where they claim that Ice Lake has lower IPC than Zen2. AFAIK there is no such a crazy conclusion. Again, I admit that down clocked CPU, which Epyc @ 3.4 GHz and Renoir @ 4.2 are, can provide slightly higher IPC.

Nope, your Icelake score is also too low. Examples have already been given but Icelake can reach up to 360+ points per clock.

That's why I use CPU with highest ST score. Ryzen 3950X has over 1300 pts and that's why I picked it.

There are a lot of examples of 3950x with higher points per clock. A 3950x can reach over 1400 points at stock.

BTW, your downclocked Epyc shows only 12% higher IPC in compare to 3950X in my table. Those poor 12% IPC gain is still far far away from Apple's A13 Lightning core 76% IPC advantage over Zen2 3950X. Even if downclocked Zen2 to 1 Hz, you cannot get higher IPC than A13.

The Epyc isn't downclocked, it's running stock, it just doesn't boost as high as a 3950x, that doesn't make it an invalid result. Also, the whole lower clock thing is a giant red herring. There are numerous examples of 3950x reaching even higher ppc than that Epyc. Here's one example with 324 ppc (higher than the Epyc example) and its not even the highest scoring or highest ppc 3950x in the database.


Also, no one is arguing that the latest Apple chips aren't the highest IPC chips around. What we're saying is that using a single mobile focused benchmark is a poor way to determine absolute IPC, you're exaggerating the lead they do have in that one benchmark, and scaling up the Apple CPUs would be more difficult than you make it sound. Not that it's impossible, but they can't just paste a bunch of them together and crank up the voltage and all of a sudden have a core that will beat everything Inte/AMD.


You don't know what you are talking about. ARM Cortex A72 which is in Raspberry Pi4 running @ 1.5 GHz (28nm) and in smartphone Snapdragon 652 around 2.0 GHz was made by TSMC with 7nm HP proces and they reached 4.2 GHz pretty easy. And those was just test samples without process tuning and binning best chips out of millions mass produced.

View attachment 31095

Maybe you missed the part in there where those test A72 cores were custom designed for high frequency and even then ran L2 and L3 cache at 1/2 and 1/4 rate.


How many people know about multi-wave propagation here? Starting another clock when signal wave is in the middle of the stage. Effectively multipling frequency without need of multiple times more stages, saving a lot of SRAM for latches between stages. Technology discovered in 90's. I guess nobody.

Maybe you should explain in detail how multi-wave propagation in digital circuits work? There are people on this forum with very technical backgrounds so feel free to go into as much depth as you'd like.
 

Thunder 57

Platinum Member
Aug 19, 2007
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Maybe you should explain in detail how multi-wave propagation in digital circuits work? There are people on this forum with very technical backgrounds so feel free to go into as much depth as you'd like.

Nah, nobody here knows anything from even the 90's. Guys, we all need to back to school.
 
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So you claim that Epyc has 321.7 pts/GHz => higher IPC than Ice Lake. Show me at least 3 good reviews where they claim that Ice Lake has lower IPC than Zen2. AFAIK there is no such a crazy conclusion. Again, I admit that down clocked CPU, which Epyc @ 3.4 GHz and Renoir @ 4.2 are, can provide slightly higher IPC. That's why I use CPU with highest ST score. Ryzen 3950X has over 1300 pts and that's why I picked it.
All of your scores are suspect. That is the problem. Your own data shows Zen 2 only have a 4% IPC advantage over Zen 1, which is just complete nonsense. You are purposely cherry picking results that fit your narrative better. As others mentioned, there are many 3950X GB runs with significantly higher single-threaded scores at the same clock speed. Yet you're purposely ignoring them and choosing low scoring runs to better fit your narrative.
 

Doug S

Platinum Member
Feb 8, 2020
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Geekbench does not scale linearly with clock speed so it will be a bit less (this is anothher reason why this graph is inheritly unfair, a 4Ghz A14 would have noticable worse score)

No benchmark scales linearly with clock speed unless it runs entirely within cache. If you double the clock rate of a CPU the main memory is the same speed as it was before, but latency has doubled in terms of clock cycles. Likewise if you cut a CPU's clock rate in half, memory latency in terms of cycles is halved.
 

Doug S

Platinum Member
Feb 8, 2020
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You don't understand basics of pipeline/stage design. Both low-power ARMs and high-speed x86 uses short 6 FO4 but from different reasons:
  • x86 uses short 6 FO4 for high frequencies obviously (with big help of HP version of process for voltage up to 1.5V)
  • ARM uses short 6 FO4 for low-voltage at medium frequency within given TDP (HD process has almost double density, huge money savings at the cost that it will never go over 4 GHz, which is non-sense in smartphone environment).
Both, x86 and ARMs tries to get as short stages as possible to get maximum frequency/performance out of it. The main difference is that x86 is limited by max Voltage and thermal density/overheating while ARMs are limited by ultra low TDP only. That's why A72 can run way over 4.2 GHz if it's manufactured with HP process.

It works also in opposite way for x86 to be able run super low TDP. AMD released Zen1 APUs with 6 W TDP. Intel also has CPU with 7 TDP or Lakefield with Sunny Cove runing close to smarphone TDP. It's pretty sad how many people here doesn't understand physics.

How many people know about multi-wave propagation here? Starting another clock when signal wave is in the middle of the stage. Effectively multipling frequency without need of multiple times more stages, saving a lot of SRAM for latches between stages. Technology discovered in 90's. I guess nobody.


Please provide your source showing the FO4 delays of recent x86 and Apple SoCs. Stanford used to have a list but I don't think it has been updated for a long time, and I doubt anyone knows the FO4 delays of Apple's SoCs.

As far as wave pipelining goes, I know HP used it for their huge off chip cache in the PA-RISC 7xxx series, to avoid taking the wire delay hit. That's not relevant for internal circuits like say a multiplier. Show us some references stating this is being used inside the core of modern designs. I could believe it might be used for cache access (especially cache that's relatively "far away" on the die, like the L3) but I'd be shocked if it is being used for logic. AFAIK none of the automated tools can handle it, it is basically asynchronous circuit design so would be on your own and have to do the timing calculations (including safety margin for process variation) by hand. I just don't buy that any x86 or ARM designs are doing this. Maybe IBM, I could see them doing something crazy like that in POWER.

Just because something has "been known since the 90s" doesn't mean it gets used. Asynchronous circuits have been known since the 50s, but even today no one does them despite the obvious performance and power benefit - because its way too damn hard (some researchers did build an asynchronous ARM once...google AMULET)
 

DrMrLordX

Lifer
Apr 27, 2000
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I told people: create your own and better IPC table. Show me how better you are.

You should not create IPC tables. You should benchmark two CPUs against one another in a large suite of software and then draw conclusions about where each CPU excels in which workloads. IPC tables are useless. IPC itself is, at best, an estimate of performance between different generations of the same hardware platform running basically the same software - for example, it's normal for people to compare IPC of Netburst designs to Core2, to show how much stronger Core2 was, but you don't really understand why Core2 was better until you look at the benchmark results.

The operative question is, "how does this CPU make my work better/faster/easier?" and comprehensive benchmarks show you that. Geekbench 5 alone does not grant you that information. It probably never will.

It's clear that most people is angry due to Apple's almost double IPC and much bigger 6xALU architecture

No. It is clear that people are angry at you for manipulating disparate data to push some ridiculous anti-x86 agenda.

In what world is BLENDER a better benchmark than SPEC? :rolleyes:

In this one? Blender is an outstanding benchmark. Many people use it to do real work. It's a great FP benchmark. We've been using CPU rendering software of various sorts to benchmark desktop CPUs for years. If someone wants to start comparing phone SoCs to desktop/workstation/server CPUs, why not ask for some Blender results? And you can compile it to run on a Mac, so the A14 Macs will give us hard numbers.

Of course I would want other software results as well before I started making comprehensive comparisons between A14 and anything desktop x86.
 

Richie Rich

Senior member
Jul 28, 2019
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Maybe you missed the part in there where those test A72 cores were custom designed for high frequency and even then ran L2 and L3 cache at 1/2 and 1/4 rate.
Maybe you missed the part where Intel uses for L3 cache lower uncore frequency as well.
Maybe you missed the part where Apple big cores runs at 2.6 GHz, little cores at 1.8 GHz and GPU < 1 GHz, so L3 SLC cache also runs with some multiplier. Apple's L3 cache is shared with GPU and NPU as well. This shared L3 cache for GPU is something AMD Renoir and Intel can only dream of. Not speaking that they have no NPU to be connected to L3. Apple is light years ahead anybody.

I admit A72 at COWOS is not 100% core copy but maybe 99% copy. Minor changes. When ARM can do this minor changes for some experimental side project like COWOS then imagine Apple with all their massive resources.

Intel and AMD should be scared not because high frequency ARMs (that's easy to do) but because chiplets on interposer. Neoverse V1 stated using HBM2E memory and coherent chiplet architecture.

Maybe you should explain in detail how multi-wave propagation in digital circuits work? There are people on this forum with very technical backgrounds so feel free to go into as much depth as you'd like.
I doubt that on this forum are people with technical background. Best people like Andrei left this forum due to permanent attacks form knowless people. Just search what happened in Graviton2 thread. How you want learn lesson #10 about multi-wave propagation when you don't know lesson #1-9 how the pipeline stages works and what is critical path length? Otherwise you would never claim that ARMs cannot be clocked to high frequencies. There is a paper regarding multi-wave you can google it.


Please provide your source showing the FO4 delays of recent x86 and Apple SoCs. Stanford used to have a list but I don't think it has been updated for a long time, and I doubt anyone knows the FO4 delays of Apple's SoCs.
I found that AMD's FPU from 2000 (Athlon XP probably) has 35.2 FO4 latency for double FP adder (in two stages probably). So single stage has 17.4 FO4 latency which means all other executions units in CPU have to be about the same length:

FPUadder_FO4_delay_stage_length_critical_path--table.pngFPUadder_FO4_delay_stage_length_critical_path--scheme.png
 

name99

Senior member
Sep 11, 2010
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Why so obsessed with clock frequency? If Apple could clock A14 to 4GHz, that would mean about 2100 in Geekbench ST - good luck Intel and AMD to match it.

Think of it this way.
This forum is populated with 10% who know what they are talking and another 90%.
Which is which?
Well, which are the ones that endlessly squawk about clock frequency?

It's useful having a bozo filter.
 

name99

Senior member
Sep 11, 2010
496
382
136
Also, no one is arguing that the latest Apple chips aren't the highest IPC chips around. What we're saying is that using a single mobile focused benchmark is a poor way to determine absolute IPC, you're exaggerating the lead they do have in that one benchmark, and scaling up the Apple CPUs would be more difficult than you make it sound. Not that it's impossible, but they can't just paste a bunch of them together and crank up the voltage and all of a sudden have a core that will beat everything Inte/AMD.

Don't treat us like idiots. You know full well that Apple chips have been benchmarked via SPEC, via browsers, via my own Mathematica tests, and all results are consistent with GB5.
To keep whining that "GB5 is a single mobile focused benchmark" says a lot more about you than about GB5 or Apple chips.
 

Hitman928

Diamond Member
Apr 15, 2012
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Don't treat us like idiots. You know full well that Apple chips have been benchmarked via SPEC, via browsers, via my own Mathematica tests, and all results are consistent with GB5.
To keep whining that "GB5 is a single mobile focused benchmark" says a lot more about you than about GB5 or Apple chips.

Let's hear it, what do you think my posts say about me, specifically?
 
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Doug S

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Feb 8, 2020
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In this one? Blender is an outstanding benchmark. Many people use it to do real work. It's a great FP benchmark. We've been using CPU rendering software of various sorts to benchmark desktop CPUs for years. If someone wants to start comparing phone SoCs to desktop/workstation/server CPUs, why not ask for some Blender results? And you can compile it to run on a Mac, so the A14 Macs will give us hard numbers.

Of course I would want other software results as well before I started making comprehensive comparisons between A14 and anything desktop x86.


That makes Blender a good benchmark for people doing Blender like tasks, and an outstanding benchmark for people actually running Blender. That doesn't make it better than SPEC, which not only tests a much wider array of FP tasks than Blender, but also tests INT which Blender doesn't really do at all.

So no, Blender is a far inferior benchmark to SPEC unless rendering is the main thing you care about.
 

lobz

Platinum Member
Feb 10, 2017
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People wanted to cheat. I remember one guy downclocked his x86 CPU to 2.6 GHz similar to Apple, probably boosted uncore and DDR mem to maximum and claimed score higher about +20% than my table. This is cheating. Apple core can also provide higher IPC at 1 GHz. GB database is full of tweaked and OC'ed systems with wrongly reported frequency. I try to use GB results from reviews as much as possible to get reasonable numbers. I stated this table is chart of IPC under normal maximum performance to avoid down clocking (cheating).
How do you still manage to trick decent people here into thinking you're actually arguing with them, while deliberately lying and 'forgetting' already established arguments/facts in this very topic after 1-2 days and going on with your insane propaganda, is totally beyond my comprehension.
 
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Apr 30, 2020
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This shared L3 cache for GPU is something AMD Renoir and Intel can only dream of. Not speaking that they have no NPU to be connected to L3. Apple is light years ahead anybody.
What do you mean? You don't think Intel or AMD are capable of sharing cache between the GPU and CPU? Most Intel iGPUs already share the L3 with the main CPU cores. Ice Lake adds a dedicated L3 to the iGPU - but it's still connected to the LLC of the main CPU cores. Don't forget about Broadwell, with its EDRAM L4 shared between the CPU and GPU as well.
I doubt that on this forum are people with technical background. Best people like Andrei left this forum due to permanent attacks form knowless people. Just search what happened in Graviton2 thread. How you want learn lesson #10 about multi-wave propagation when you don't know lesson #1-9 how the pipeline stages works and what is critical path length? Otherwise you would never claim that ARMs cannot be clocked to high frequencies. There is a paper regarding multi-wave you can google it.
No one is claiming that ARM CPUs cannot be clocked to high frequencies. We're claiming that an ARM implementation that TARGETS a ~2.5 GHz design frequency is not likely to be able to scale up to 4+GHz. It's not a matter of simply cramming more volts into the CPU or replacing a logic library here and there. There is a A LOT of work required to shift clock speeds up that high.

Look at AMD's Llano vs Richland APUs. Both on the same GF 32nm SOI process. Llano could barely wheeze out 3GHz, while later Richland APUs on a different architecture pushed that to 4.4GHz.
 
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itsmydamnation

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Don't treat us like idiots. You know full well that Apple chips have been benchmarked via SPEC, via browsers, via my own Mathematica tests, and all results are consistent with GB5.
To keep whining that "GB5 is a single mobile focused benchmark" says a lot more about you than about GB5 or Apple chips.
If that's what you took from his post you just made yourself actually look like an idiot because you obviously lack comprehension. Is your name Donald?

User insults are not allowed. Additionally, this is not
the P&N forum. If you want to talk about Donald, post
there.

AT Mod Usandthem
 
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DrMrLordX

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So no, Blender is a far inferior benchmark to SPEC unless rendering is the main thing you care about.

Except that Blender can't be gamed by compilers (oops) and that unlike SPEC, Blender is actually multithreaded while SPEC just loads multiple instances of single-threaded benchmarks. Would you like to be the next one who gets to lecture the forum on why reviewers like Anandtech should scrap their entire benchmark suite and just run SPEC and Geekbench 5?
 
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Doug S

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Except that Blender can't be gamed by compilers (oops) and that unlike SPEC, Blender is actually multithreaded while SPEC just loads multiple instances of single-threaded benchmarks. Would you like to be the next one who gets to lecture the forum on why reviewers like Anandtech should scrap their entire benchmark suite and just run SPEC and Geekbench 5?

If Anandtech was running Blender as their only benchmark I would be saying they need to scrap that and go with a wider variety of tests. Either SPEC or GB would be superior to that single benchmark. I'm not saying SPEC or GB are better than an entire benchmark suite, of course they aren't, I'm saying either is better than Blender alone. It should be obvious to anyone with half a brain that running a benchmark suite that contains a couple dozen tests that all do different things is better than running a single test that does only one thing. Getting a couple dozen numbers to look at is better than getting one number to look at.

SPEC2006 has had compiler writers break a couple of the benchmarks, but those benchmarks were fixed/removed in the next version and AFAIK none of SPEC2017's tests have been broken yet. If you want to look at a single benchmark number that's game-proof, instead of Blender look at the gcc/llvm numbers in SPEC/GB5 and ignore the rest. Compilers have lots of difficult to predict branches and a large icache footprint, and provide probably the closest analogue to modern browser/GUI code.
 
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itsmydamnation

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So AMD claimed they have wider execution for Zen3 ( we will have to wait and see if more issue ports or just more capability per port) and it only accounted for ~3% of the ~20% IPC increase. With the biggest gains from decode and load+store. This must be really disappointing news for the arbitrary unit counters :eek:o_O:screamcat:
 

itsmydamnation

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What does more "capability per port" mean in this context?
so AMD has 4 ALU ports but not all operations exist on all ports. AMD could increase number of issue ports or make each ALU more symmetric/capable . Both could be classed as widening the execution engine. My bet is more issue ports, it is probably cheaper to have extra simple ALU's that can absorb simple arithmetic/logic ops leaving more fully functional ALU's to handle complex ops then it is to make all ALU's handle all complex ops for example.
 

DrMrLordX

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Apr 27, 2000
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So AMD claimed they have wider execution for Zen3 ( we will have to wait and see if more issue ports or just more capability per port) and it only accounted for ~3% of the ~20% IPC increase. With the biggest gains from decode and load+store. This must be really disappointing news for the arbitrary unit counters :eek:o_O:screamcat:

Oh don't worry. Facts never stopped them.

Is your day job political spin?

No. Is yours?

How many people posting here honestly looked at anything I posted and thought, "gee this man is endorsing benchmarking a CPU with only Blender" when I have gone out of my way multiple times to indicate that any CPU-to-CPU comparison should involve multiple different applications, preferably those relevant to the target readership.

How could anyone possibly post here on Anandtech and not be familiar with how CPU benchmarking is normally carried out on a site like AT? Anyone who has followed AT over the decades should immediately be able to spot the problem with an IPC list that uses only one data point as its basis.

This isn't even remotely true.

Elaborate. I was upbraided in the Graviton2 thread for thinking otherwise.
 
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