TLC, 3 bit and 8 voltage states?

[Hulk]

I'm missing something quite simple here but can't seem to work it out. SLC stores one bit of information and has two voltage states. MLC stores 2 bits of data and has 4 voltage states. But TLC stores 3 bits and has 8 voltage stages? Seems like it should only require 6 voltage states, or with 8 voltage states could store 4 bits?

 

[sub.mesa]

Four states for MLC (2-bit)
0 + 0
0 + 1
1 + 0
1 + 0

Eight states for TLC (3-bit)
0 + 0 + 0
0 + 0 + 1
0 + 1 + 0
0 + 1 + 1
1 + 0 + 0
1 + 0 + 1
1 + 1 + 0
1 + 1 + 1

So it is not 2+2+2 but 2^3.

Likewise, 4-bit QLC would require 2^4 = 16 voltage states.

 

[Hulk]

I'm feeling really dense here In fact I can hear Rutgers calling for their degree back... I'm still seeing 8 values when only 6 are needed. If there are 3 bits in a cell then you only need write or read 6 values. I know my reasoning is wrong but I can't see it!?

 

[Charles Kozierok]

I'm feeling really dense here In fact I can hear Rutgers calling for their degree back... I'm still seeing 8 values when only 6 are needed. If there are 3 bits in a cell then you only need write or read 6 values. I know my reasoning is wrong but I can't see it!?

You're counting the 0 or 1 in each cell to get 2+2+2=6 but there are 2*2*2=8 combinations as sub mesa pointed out.

Think of it in decimal. Three digits means 10*10*10 possible numbers, not 10+10+10 possible numbers.

 

[Hulk]

I understand that there are 8 binary voltage values being stored. But only 6 are being used in the TLC NAND. That is what is confusing me. If you can write 8 discrete values why can't you read 8 discrete values and be able to store 4 bits on information?

SLC - Writes/Reads 2 discrete values and is good for 1 bit
MLC - Writes/Reads 4 discrete values and is good for 2 bits
TLC - Writes/Reads 8 discrete values but it good for 3 bits?

 

[Charles Kozierok]

TLC uses eight levels. Part of the confusion is that the name is stupid.. it's called "triple level cell" implying that there are three voltage levels, but there aren't.

If you can write 8 discrete values why can't you read 8 discrete values and be able to store 4 bits on information?

Because 4 bits of information requires 16 discrete levels. Remember, each of the bits is independent of the others. Each can be 0 or 1. So there are 16 combinations for the 4 bits.

8 levels would work to store 4 bits if you could store 4 different voltage values in a cell. Say, the cell had 4 compartments, and in each one you could put a 0 or a 1.

But it doesn't work that way. Each cell is a single floating gate and can only store one voltage figure. That single voltage level has to be able to represent 16 different possibilities in order to represent 4 bits, so you would need 16 possible voltages.

 

[Hulk]

Okay I understand that each level in the TLC cell can be programmed to a "0" or a "1."
In total you can 8 discrete values that can be written and read. 2^3 permutations. I understand that.

What I don't understand is that I thought a bit of data is either "on" or "off." If you have 8 states available then can't you store 4 bits of data?

As I wrote above with SLC you store 1 bit with two discrete values.
With MLC you store 2 bits with 4 discrete values. Again each bit requires two discrete values.
But with TLC you store 3 bits of data with 8 discrete values. Suddenly each bit now requires 8/3 discrete values to store it? Only 6 discrete values are required though?

I'm not trying to be dense here. Perhaps it's late and I'm tired and not thinking straight but it's not clicking for me.

 

[imagoon]

Okay I understand that each level in the TLC cell can be programmed to a "0" or a "1."
In total you can 8 discrete values that can be written and read. 2^3 permutations. I understand that.

What I don't understand is that I thought a bit of data is either "on" or "off." If you have 8 states available then can't you store 4 bits of data?

As I wrote above with SLC you store 1 bit with two discrete values.
With MLC you store 2 bits with 4 discrete values. Again each bit requires two discrete values.
But with TLC you store 3 bits of data with 8 discrete values. Suddenly each bit now requires 8/3 discrete values to store it? Only 6 discrete values are required though?

I'm not trying to be dense here. Perhaps it's late and I'm tired and not thinking straight but it's not clicking for me.

To quote mesa: with a mod from me. "hypothetical tlc"

Eight states for TLC (3-bit)
0 + 0 + 0 .1 volt
0 + 0 + 1 .2 volt
0 + 1 + 0 .3 volt
0 + 1 + 1 .4 volt
1 + 0 + 0 .5 volt
1 + 0 + 1 .6 volt
1 + 1 + 0 .7 volt
1 + 1 + 1 .8 volt

There is all 8 of your states and 3 bits per state with 8 hypothetical voltages.

Can you explain where you keep getting 6 states from?

 

[Hulk]

There are definitely 8 states in a 3 level NAND cell. No question about that, no confusion there.

I think my confusion is coming from how the NAND is actually programmed and read. Can you tell me how SLC and MLC is programmed and read?

I would think that with SLC a voltage would be applied to the cell. When read the voltage would either be there or it would not be there. 0 or 1.

How can 4 values be programmed and read from one MLC cell?

And thanks for hanging in there with me.

 

[Avalon]

What I don't understand is that I thought a bit of data is either "on" or "off." If you have 8 states available then can't you store 4 bits of data?

Yeah, each bit can be either off or on (1 or 0). But, the cell was designed to only have a combination of 3 bits. Each of the three can independently be off or on, giving you a total combination of 8 unique values.

I think where you're getting confused is in thinking a minimum amount of states are required for X amount of bits. It's the other way around. A minimum of X amount of bits are required to have a Y amount of states, in this case 3 binary bits are required to have 8 states.

Since we're talking binary here (off or on), there would be two states if we had a 1 bit cell.

 

[Hellhammer]

There are definitely 8 states in a 3 level NAND cell. No question about that, no confusion there.

I think my confusion is coming from how the NAND is actually programmed and read. Can you tell me how SLC and MLC is programmed and read?

I would think that with SLC a voltage would be applied to the cell. When read the voltage would either be there or it would not be there. 0 or 1.

How can 4 values be programmed and read from one MLC cell?

And thanks for hanging in there with me.

A cell is programmed by applying a high voltage that allows electrons to tunnel through the silicon oxide to the floating gate. That creates a charge in the floating gate. The amount of charge defines the state and bit output of the cell (each output has their own state, obviously).

When reading a cell, you just apply different voltages and wait for the cell to respond. When it responds, you'll know the state its programmed into and the bit output (i.e. you've just read the data stored in the cell).

 

[Charles Kozierok]

Okay, let's suppose we start with a regular SLC. It can only have two levels, a positive voltage and zero, representing a logical 1 or 0, a single binary digit.

But we need to realize that this is only theoretically true. In practice, it's a bit different.

A flash cell is sort of like a regular transistor but with an extra gate that is separated from the normal one and electrically isolated. Like so:

This image conveniently describes how the floating gate is charged. So when you write a "1", you are programming in this voltage. Let's say for convenience that the voltage level for a 1 is 3V. (It's much lower than that in practice.) A 0 bit would be 0V.

Now, when you want to read the cell, it's not really going to have either 3V or 0V in it. Because of real world issues like leakage and so forth it will have something you hope is close to 3V for a 1 and close to 0V for a 0. You can arbitrarily decide that anything above 1.8V is a 1, and anything below 1.2V is a 0, and if it's between 1.2V and 1.8V, then you aren't really sure and you're going to call it an error and use error recovery rather than trusting the value in the cell.

But wait, the engineer says... why only use a single positive voltage? Instead of 3V for 1 and 0V for a 0, let's program two bits as follows:

0 0 = 0V
0 1 = 1V
1 0 = 2V
1 1 = 3V

So instead of always sending 0V or 3V into the gate, you can now send 0V, 1V, 2V or 3V. There are now four voltages which can represent two bits.

Again, those ideal voltages won't actually be seen -- instead, you have to define ranges around them that will be interpreted as those values. But now you have much less room around each value -- instead of 3V separating a 1 and a 0, you have only 1V separating any two nominal values. Thus, the chance of error is higher, and that's why MLC is less reliable than SLC. The need to be able to precisely program different voltage levels also, I believe, leads to reduced longevity.

With TLC it's the same, only now you are dividing the possible voltages even more finely, so it gets even more tricky.

 

[Hulk]

First of all thanks to everyone.
Second, Charles your post provided my "Eureka!" moment. Thank you for taking the time to post.

For some reason I was thinking that the MLC or TLC cell could simultaneously store all of the states simultaneously. I never really thought about how the silicon actually worked. The cell of course can only store one voltage at a time. And from that information follows my understanding.

When you read the single voltage from the TLC cell (or any type of flash cell) this value has to provide you with the value of each of the 3 bits stored in that cell. Three bits of data requires a 3 digit binary number, and a 3 digit binary number has 8 different states.

And to store 4 bits of data in a cell you would need a binary number with 4 digits, and there are 16 permutations in a 4 digit binary number. Yes I get it.

Now for a follow up question.

It would seem that a much lower voltage could be applied to SLC vs. MLC NAND and that is why the endurance of SLC is so much higher. Plus you have a much wider range of voltage fluctuation that you can handle and still accurately read the cell contents. Same goes for MLC vs. TLC.

I assume that NAND is binned in a manner similar to other silicon and there are part of a wafer, or wafers that are very high quality and some that are low quality. And I would think that high quality would mean NAND that is very repeatable when reading and writing particular voltages.

So, is part of the cost savings in using the NAND in MLC or TLC "used up" in the fact that higher quality and hence more expensive NAND must be used in MLC and more so in TLC? I guess this starts to swerve in that area of binning which has always been highly guarded by the manufacturers. One manufacturer can toss low quality NAND into a TLC drive and end up with really low endurance and give TLC a bad name. When it's really the fact that the manufacturer just got cheap right?

It also seems as though the law of diminishing returns comes into play in a big way here. When you move from SLC to MLC you get a substrate savings of 50% while doubling the number of state read/write values.

But when you move from MLC to TLC you only get a substrate saving of 33% but the increase in read/write states still doubles. So there seems to be a need for very high quality NAND as compared to MLC. Could this, among other factors, be the reason we are seeing the TLC Samsung SSDs being as expensive as many MLC SSDs? They do seem to be a bit more cost effective in terms of performance/dollar than the MLC drives, but not the 33% the substrate savings initially seemed to indicate.

Learned a lot. Thanks.

 

[Hellhammer]

It would seem that a much lower voltage could be applied to SLC vs. MLC NAND and that is why the endurance of SLC is so much higher. Plus you have a much wider range of voltage fluctuation that you can handle and still accurately read the cell contents. Same goes for MLC vs. TLC.

That's what eMLC essentially is. Lower voltages cause less stress on the oxide but the downside is that the tunneling time (i.e. program time) is also longer, which results in slower performance.

I assume that NAND is binned in a manner similar to other silicon and there are part of a wafer, or wafers that are very high quality and some that are low quality. And I would think that high quality would mean NAND that is very repeatable when reading and writing particular voltages.

That's correct. Usually the dies at the center of the wafer are of the highest quality.

But when you move from MLC to TLC you only get a substrate saving of 33% but the increase in read/write states still doubles. So there seems to be a need for very high quality NAND as compared to MLC. Could this, among other factors, be the reason we are seeing the TLC Samsung SSDs being as expensive as many MLC SSDs? They do seem to be a bit more cost effective in terms of performance/dollar than the MLC drives, but not the 33% the substrate savings initially seemed to indicate.

I believe the biggest reason for the SSD 840 pricing is the current state of the market. Samsung is the only manufacturer with a TLC NAND based SSD, so why would they price it substantially below MLC based drives when they can milk nice profits off of it by making it just a little cheaper.