Tightest timings/best divider on IP35-E

[brencat]

Hi gang. I'm currently in the RAM OCing stage of my new built after settling on a nice stable 3.25ghz core speed (325 x 10). I'm using 2 x 1gb + 2 x 512 Crucial Ballistix PC2-6400 sticks and Vista-32 Home Premium (see sig for more PC info).

Already tested 1:1 and 1:1.2 dividers at 5-5-5-15 and 4-4-4-12 timings, and am now working my way up hoping to test the rest of them. Currently memtesting the 1:1.25 divider (406 FSB equivalent on RAM) with 4-4-4-12 @ 2.0v while at work. At each step, I have noticed a decent speed increase especially in SP1M runs.

Looking ahead, what is the tightest timings any of you have been able to run with 4 slots populated? Assuming I pass at least 4 hrs Orthos, etc. at this speed, I will probably try 3-3-3-9 timings at this 1:1.25 divider.

Just wondering are any of you running 3-3-3-9 using dividers with 4 RAM slots filled and if so, what has been your experience so far?

 

[Thund3rb1rd]

when you get done OCin' can you do a run with 3dMark06 ?
I have nearly identical system (cpu, ram, mobo, os), only difference is my OCed 8600gt.
I want to see how much performance I'll get out of a video upgrade.

 

[brencat]

Originally posted by: Thund3rb1rd
when you get done OCin' can you do a run with 3dMark06 ?
I have nearly identical system (cpu, ram, mobo, os), only difference is my OCed 8600gt.
I want to see how much performance I'll get out of a video upgrade.

With last night's run using 1:1.2 divider (396 FSB equivalent on RAM) @ 4-4-4-12 timings, my SP1M avg for 5 runs was ~ 19.3 sec, and 3DMark06 score was 10781.

I use the freeware version of 3D06 so bear in mind that score is at 1280x1024 rez, no AA.

 

[SerpentRoyal]

I could push my RAMs up to 476MHz/4-4-4-12-2T with 2.1Vdimm...same as your configuration.

 

[BonzaiDuck]

My two-cents-worth, and it's been discussed here in other threads among me, JustaGeek and NefariousCaine:

I have a 2GB kit of Crucial Ball'x DDr2-1000's (aka PC2-8000). I've seen one person able to run them at timings similar to 4,4,4,9 -- prabably at 2T command-rate at the 1,000 Mhz speed. He also had his VDIMM voltage set to 2.2V -- the warranty-recommended voltage spec'd by Crucial.

Let's suppose you start at a 1:1 divider with the stock timings and a voltage set to "auto" or at least below the median value (somewhere around 2.0V?) As you go up in FSB, you'd have to increase the voltage, assuming that the timings were fixed.

On the other hand, you could find an FSB at 1:1 that is "comfortable" for your processor, and as you tighten the memory timings, you would have to increase the memory voltage also.

I'm fond of the Crucials for a similar reason to being fond of OCZ Platinum DDR-400 (2,3,2,5) modules. I can run them at 700+ Mhz, with the voltage at the 2.2V limit, and timings of 3,3,3,6,1T. It gets even better, because I can lower the bank-cycle-time from its default of 21 to a new setting of 9 -- with a huge gain in bandwidth.

Reducing the number of clock-cycles required to perform a single memory operation has the same effect on bandwidth that brute-force increases in frequency have. If you use a different divider to get the memory to run toward its spec, the timings will be looser, and, anyway, you're adding clock-cycles to the same time period that can't advantage the processor, since its FSB would be lower.

We said that there was a trade-off between these various scenarios. It may be that there is a marginal bandwidth improvement with the high-Mhz/loose-latency memory settings, but not much. Also, you can lower the VDIMM voltage for looser timings, even at higher FSB, but as you increase the FSB again, you'll need to increase voltage to maintain those settings over a new range.

That's why I would look for the memory modules that allow for the tightest latencies, while spec'd for either DDR2-800 or DDR2-1000 operation. Sometimes, it's a crap-shoot. You can find two sets of memory (different manufacturers and parts) that run at a certain speed and the same default latencies, but one set run at lower speeds might only allow the same latency settings, or looser settings than what the other pair can run at -- given the same -- and lower -- FSB.

Same for lower-spec'd memory modules. You might be able to find DDR2-667's which run at their lowest possible settings without fail as you raise the FSB and run them above 667. But even if you could run the DDR2-667's at close to 800 speed, you'd still find a point somewhere such that the latencies needed to be loosened to go any further, and/or the voltage needed to be increased.

Buying high-speed memories, even if you find it more practical to run them at lower speeds, may have an advantage for the near future if your mobo is spec'd for higher FSB's than the processor, and the time for higher-FSB processor releases comes nearer. However, "ceteris paribus" -- you hope that socket designs will remain the same. And if you have to switch mobos, you would hope that the new mobo runs DDR2 versus DDR3.

 

[BonzaiDuck]

PS -- for Brencat --

3DMark06 = 11,465 -- freeware version, 1280 x 1024

BFG 8800 GTS 640MB
Q6600 @ 3.15 Ghz
FSB = 1,400; DDR=700; timings: 3,3,3,6,1T, tRC=9
1:1 divider and CPU_FSB = 350 Mhz (On-ly . . . 350!!)
Everest Ultimate "read" bandwidth = 9,750 MB/s

 

[BonzaiDuck]

[That's "up" from 10,565, timings 3,4,4,8, 715 Mhz.]

I've run these Crucials with all four slots filled (2 kits) at 3,4,4,8,2T and at 3,3,3,6,2T

That's the problem with four slots: 2T command-rate pretty inevitable, thus -- drop in bandwidth.

Some have said that even 4GB 2x2GB kits from G.SKILL need 2T -- "probably for the density." Again, this also may be a function of voltage: you can either "get 'em there" at or before the recommended warranty voltage, your you can't. And if you can't, risk increases as you try to do it anyway.

 

[brencat]

Hi Bonzai...thx for your reply. I am trying to find that "balance" you refer to of brute force vs. optimal timings and am experimenting with all the dividers so I can put actual numbers on paper and figure that out. I have to say my system felt the snappiest so far using the 1:1.2 divider but I benched 3DMark06 higher (10826) and SP1M 0.3 sec faster at 1:1.25 4-4-4-12 2T, which is where I left it last night. PC is memtesting 1:1.5 divider (488mhz RAM) @ 5-5-5-15 2.0v while I'm at work right now and I'll bench it tonight.

FYI, I tried 3-3-3-9 2T and 3-4-3-9 2T timings using the 1:1.2 divider (i.e. 390 mhz RAM speed equivalent) and it was a POST but no windows boot situation using 2.2v. I then upped MCH/ICH volts 2 notches each and still no windows boot. So, I put CAS3 on hold for now. Afterward, I realized I never tested 3-3-3-9 and 3-4-3-9 at 1:1, which I will do tonight when I get home from work.

Bear in mind I have all 4 slots populated and am also using Vista, which can negatively impact some mobos' performance but Abit IP35-E that I have seems to handle it fine so far.

- What mobo do you use?
- Are you on XP or Vista?
- Did you also have to up MCH/ICH voltage to run 3-3-3-6 1T @ 2.2v ?
- Is there a formula for calculating optimal Bank Cycle time given the other 4 timings? (in other words, how did you know you could lower yours from 21 to 9) ?

Edit: Looks like you posted before I did...in addition to above questions, what MCH/ICH did you use for 3-4-4-8 2T and 3-3-3-6 2T when all 4 slots were filled? Thx!

 

[BonzaiDuck]

There is a "memory tweaking guide for DDR2" I found a couple weeks ago. I've been looking into other "advanced timing" settings. Most of the other "advanced timings" can be tweaked, but have varying impact on stability with little impact at all on bandwidth. I don't have the URL for that guide at my fingertips at the moment, but another place to check for similar information is the "Lost Circuits' BIOS guide on the web. (not sure if it is www.lostcircuits.com or .net -- but you can find it.)

For DDR2, tCL (CAS) is over-rated for bandwidth sensitivity, but it has medium to high impact on stability (thus, voltage adjustments, FSB adjustments, etc. There are thresholds . . . ) tRCD -- the second "basic" timing -- has medium impact on stability and high impact on bandwidth. tRP has medium to low impact on stability, and low impact on bandwidth. tRAS -- medium impact on stability, low impact on bandwidth -- BY ITSELF.

The conventional formula suggests that tRAS >= tCL+tRCD. Also, that tRC >= tRP+tRAS.

So if you can lower tCL and especially tRCD, you can then lower tRAS, but the only significant impact on bandwidth would be the first two latencies tightened. HOWEVER, with lower tRAS, and same or lower tRP -- you can lower the bank-cycle-time -- tRC.

tRC can't be LOWER than the sum of tRP and tRAS, and doing so would cause data corruption. It CAN be EQUAL TO the sum -- with an even safer setting pretty much assured to be tRP+tRAS+1.

I found this to be true: at the high-end fo FSB and voltage settings for a certain fixed tCL (and just before you'd need to loosen tCL to get higher FSB), the "+1" setting for tRC is stable, while the tighter setting may cause instability. If you drop FSB by a few notches, then the tighter setting is also stable.

So tCL offers modest increases in bandwidth for tighter settings; tRCD offers bigger increases in bandwidth; and the bandwidth improvement for tRC is even greater. And if you can lower the other latencies that have little impact by themselves on bandwidth, you can also tighten tRC -- which has a big impact.

I'm using STriker Extreme 680i board with BIOS revision 1303 (which "disappeared" from ASUS web-site when they introduced v. 1305). I'm using XP MCE 2005. I"m not sure how XP versus VISTA would affect these hardware settings, but it's a possibility. I just don't know, and you'd ask yourself why -- why would it even make sense?

IN my over-clocking pursuits, I incrementally increased 1.2VHT(MCH), CPU_VTT, NB(core) and SB(core). I had gone up between two and three notches on these voltages, maybe to 1.35, 1.45 and 1.45 respectively while leaving SB at 1.5 (showing 1.52 monitored, just as in "Auto" setting for SB). I discovered when I finally found the "sweet spot" that I could knock these back down nearly to what "auto" would give: 1.3 VHT, 1.35 VTT and 1.35 NB.

Frankly, I think I could drop them each another 0.05V, but these settings aren't very high, and the system is running very well. I shouldn't have to worry at these settings that they've been "over-volted".

HOWEVER -- I DID have a stable 3,3,3,6,1T setting at 1,333 FSB and 667 DDR, with ALL the miscellaneous voltages on "Auto." And I'm quite sure that you could tighten tRC to the same limits with no implications for those voltage settings. That's been born out by the same basic timings at 700+ Mhz.

 

[BonzaiDuck]

. . . sorry about the multiple posts (and they're verbose, too . . ).

There is one more interesting hitch to this. As I said, the setting for tRAS should be tCL+tRCD -- BY CONVENTIONAL (DDR1 (?) ) WISDOM.

NefariousCaine, with essentially the same DDR2 Crucials that I have (except that they were DDR2-800's) was able to use 3,3,3,3. Yes! 3,3,3,3 -- and I think he said at 1,333FSB.

His bandwidth benchies with Everest seemed to be about 300 MB/sec better than mine, at least on the "read" test, and several hundred better on the "write" test (maybe it was "copy," but I think it was "write.")

My initial "stick-the-toe-in-the-water" tests showed no change in bandwidth with tRAS at 5 as shown by MEMTEST86, but Nefarious wouldn't lie, and he showed "screenies."

Since I'm reveling in my gains "under conventional wisdom," I'm also wondering about stability with this "rad and awesome" setting, or possible data-corruption.

But there's something in DDR2 technology called "additive latency" which refers to tCL, and might have an impact on tRAS. From the diagrams, it looks as though DDR2 "extends" CAS so that it "overlaps." I still need to read through a very technical white paper on DDR2 to get a better idea . . . . In meantime, this is about as good as I'd hoped for having spent more than necessary on Crucial memories. I could've saved some ducats and bought the DDR2-800's.

My SiSoft Sandra benchies may be a little more modest, showing "just behind" a dual-core setup, 975 chipset and DDR2-1000s, which you would think were run at a divider with stock latencies. The results are a sliver of difference, almost neck-and-neck photo-finish. But SiSoft is the first to say "these are synthetic" and may not reflect true performance. In comparison to Q6600 systems paired with DDR2-667s, my settings just blow the comparison systems out of the water, and look as good as a 30 to 50% improvement in speed and bandwidth over those systems. But I'd only increased my memory speed by 5% over the rated speed of the comparison systems' DDR2's. You'd think that the difference between 667 and 800 with 1:1 ratio would be 20% at the same latency settings --so it's either a "wash" between my DDR "700" and 800 Mhz, or I'm actually a margin better off.

Another SiSoft "estimated bandwidth" measure reports mine at 13,000+ MB/s.

 

[brencat]

Thx a ton Bonzai. Let me also say this has been one of the most informative, detailed, and useful posts I've seen in a while on AT.

So based on your info, if my system likes 4-4-4-12 2T at both 1:1.2 and 1:1.25 (which it does), it certainly sounds like I should be able to tighten timings to 4-4-4-8 or 4-4-4-9, and set tRC from Auto to 13 or 14 assuming system is stable with tRAS at 8 or 9. At a minimum, I guess I can bring this down to 17.

Abit boards tend to be pretty aggressive with subtimings when set to Auto so there's no way for me to know what the mobo is using for tRC currently. I guess I'll just have to mess with it and see what happens. I memtest every setting before booting to windows anyway.

Regarding Vista vs XP, reason I mentioned it is that 3DMark06 scores seem to be lower when running in Vista (i.e. 13000+ scores in XP tend to be sub 12000 in Vista). Also, Vista apparently is much less tolerant of system instability (especially RAM instability) relative to XP.

If you can think of anything else, please post it. Again, I really appreciate the information. :thumbsup:

 

[BonzaiDuck]

Looking at your tests, I don't see why you shouldn't at least ATTEMPT tighter timings on the "other-than-1:1" dividers. I'm willing to bet, though, that the memories won't be as elastic to lower settings as they would at lower FSB speeds -- whatever the divider used.

With my Crucial Ball'x, I found lab-test reviews that gave an entire schedule of tested latency settings at various speeds. They showed that 3,4,4,10 would work below DDR2-775 (more or less -- and this is all "recollection" by a 60-year-old.) They showed that 4,3,4,8/9 would work between that limit and about DDR2-840 -- when the stock settings for DDR2-800 were about 4,4,4,12 (I think).

The only thing to do is "try." I think I had one over-clock configuration with a lower CPU multiplier where I'd gone to DDR2-804 (but 1:1 !! (chuckle)) and more or less proven the review assertions about these modules.

But there's only one way for you to find out. And -- yeah -- MEMTEST everything before you slip into a Windows reboot. Hopefully, you can avoid needing to reset the CMOS, too.

I'm pretty sure, though -- willing to bet -- that whether you choose a different divider than 1:1 -- you'll pretty much be following the schedule of stable settings I saw in that review.

 

[MadScientist]

Thanks Brencat for starting this thread, some good info from the Duck.
Duck,
I'm currently setting up a rig for my son for Christmas, if my 8800 GT from Dell gets here, with 4 x 1 GB DDR2 (2 matched sets) of PC6400 Ballistix. I'm not sure if it's my ram or the MB's (another Abit IP-35E) memory controller but they will not run at 4-4-4-12-2T, 2.2V, at 800 (400) Memtest86+ V1.7 stable, fails test 5 on first pass. By dropping down just a hair to 798 (399) they pass test 5 and test 8 looped for 1 hour. By just changing the Tcl from 4 to 5 I was able to reach 488 at 2.1V and 509 at 2.2V Memtest86+ stable. When I use only 2 GB of either set it passes Memtest86+ at 4-4-4-12-1T, 2.2V, above 400.
So Duck, do you think it's some flaky ram or possibly my MB doesn't like 4 x 1GB Ballistix at these settings?
I'm going to also try your settings. Is this what you are currently running: 700 (350), 2.2V, 3-3-3-3-6-2T, tRC of 9? I have not decided yet on what oc to use for this CPU. So far this is some that were Prime95 stable, Small FFts, for 3 hours. I'm going to test them again when and if I get the 8800 GT from Dell for 8 hours. I used Coretemp 0.95.4, hacked to work with Vista 64, to monitor temps.
Highest stable oc at stock voltage:
CPU Speed---FSB-----Bios V----CPUZ V(idle)---CPUZ V(load)---Temp(idle)---Temp(load)
3.285 Ghz----365----1.2375------1.192-------------1.152------------29 C----------44 C
Temps remained stable after about 1 hour.
3.510 Ghz----390----1.3175------1.272-------------1.240------------32 C----------52 C
3.600 Ghz----400----1.3575------1.312-------------1.272------------34 C----------58 C

Rojak's Bios Optimization Guide was once very useful, but the free version needs updating.

I have those ram formulas scribbled in my Epox 9NPA+ Ultra MB manual from a few years ago. I probably got them from one of Rojak's old Bios guides. They are for ddr. Are they still valid for ddr2?
I have, if I can read my writing, Tras = Tcl + Trcd + 2 and Trc = Tras + Trp

Q6600 GO stepping
Abit IP35-E
Geforce 7600 GT
4 x 1 GB Crucial Ballistix PC6400 DDR2-800
Vista Ultimate 64
2 x Maxtor 300 GB SATA HDs
Samsung SH-S203B SATA DVD Burner
Corsair 620W PSU
Cooler Master Hyper TX2 HS/fan
Antec 900 case

 

[brencat]

** A portion of this post appears on pg 99 in the IP35-E thread in AT Mobo discussion **

I tried 5-4-4-9 timings @ 1:1.5 (488 RAM speed) but no go. Specifically 2.05v errors immediately, 2.1v fails Test #4 on first pass, 2.1v with MCH +2 bumps also errors Test #4, and 2.2v with default MCH errors on Test #5 on 2nd pass. Did not try 5-4-4-12 but will revisit that one later.

But I did have luck with 4-4-4-8 @ 1:1.25 (406 RAM speed) @ 2.05v. (Note that I gave it the extra 0.05 juice just to be sure). With tRAS 4 points tighter, it improved my SP1M score by ~ 0.2 sec and system feels really crisp. 3DM06 was modestly higher:

1:1.25 @ 4-4-4-12, 2.0v: SP1M 19.22--19.30--19.30--19.19--19.25. 3DMark: 10826
1:1.25 @ 4-4-4-8, 2.05v: SP1M 19.09--19.07--19.05--19.05--19.03. 3DMark: 10830

I'm currently memtesting 1:1.25 @ 4-4-3-9, 2.05v. This looks promising as bandwidth has improved some 125mb/sec over 4-4-4-8 setting.

@ Bonzai... I checked but unfortunately tRC is not an adjustable setting in the IP35 bios. In addition to the main 4 and the command rate, we can tweak tRFC, tWR, tWTR, tRRD, and tRTP. You 680i guys have an advantage when it comes to RAM OCing!

 

[MadScientist]

Originally posted by: brencat
@ Bonzai... I checked but unfortunately tRC is not an adjustable setting in the IP35 bios. In addition to the main 4 and the command rate, we can tweak tRFC, tWR, tWTR, tRRD, and tRTP. You 680i guys have an advantage when it comes to RAM OCing!

Scratch that one, one less setting to worry about. I assumed, since my nforce4 MB also has it, that the IP35-E did to. I didn't check since I'm juggling 1 video card between 2 computers. I'm dissapointed with the bios on the IP35-E. It does not show what the ram settings are in Auto. Maybe by bios V20 Abit will fix this. My nforce4 board also has 9 ram ratio settings, but I'm comparing apples to oranges, a ddr MB to a ddr2 MB.

 

[Thund3rb1rd]

Originally posted by: brencat
With last night's run using 1:1.2 divider (396 FSB equivalent on RAM) @ 4-4-4-12 timings, my SP1M avg for 5 runs was ~ 19.3 sec, and 3DMark06 score was 10781.

I use the freeware version of 3D06 so bear in mind that score is at 1280x1024 rez, no AA.

3.15ghz @ 1.465 vcore
RAM @ 394mhz 4-4-4-12-2T
AVG 5xSP1M = 19sec flat
3dMark06 (1280x1024, no AA) = 5529 :thumbsdown:

But, I got good deals on all of the parts for this system.
My main concern was 'how good will this thing upgrade'. Which is what bit me in the butt with my last build, no upgradeability.

 

[BonzaiDuck]

Originally posted by: MadScientist
Thanks Brencat for starting this thread, some good info from the Duck.
Duck,
I'm currently setting up a rig for my son for Christmas, if my 8800 GT from Dell gets here, with 4 x 1 GB DDR2 (2 matched sets) of PC6400 Ballistix. I'm not sure if it's my ram or the MB's (another Abit IP-35E) memory controller but they will not run at 4-4-4-12-2T, 2.2V, at 800 (400) Memtest86+ V1.7 stable, fails test 5 on first pass. By dropping down just a hair to 798 (399) they pass test 5 and test 8 looped for 1 hour. By just changing the Tcl from 4 to 5 I was able to reach 488 at 2.1V and 509 at 2.2V Memtest86+ stable. When I use only 2 GB of either set it passes Memtest86+ at 4-4-4-12-1T, 2.2V, above 400.
So Duck, do you think it's some flaky ram or possibly my MB doesn't like 4 x 1GB Ballistix at these settings?
I'm going to also try your settings. Is this what you are currently running: 700 (350), 2.2V, 3-3-3-3-6-2T, tRC of 9? I have not decided yet on what oc to use for this CPU. So far this is some that were Prime95 stable, Small FFts, for 3 hours. I'm going to test them again when and if I get the 8800 GT from Dell for 8 hours. I used Coretemp 0.95.4, hacked to work with Vista 64, to monitor temps.
Highest stable oc at stock voltage:
CPU Speed---FSB-----Bios V----CPUZ V(idle)---CPUZ V(load)---Temp(idle)---Temp(load)
3.285 Ghz----365----1.2375------1.192-------------1.152------------29 C----------44 C
Temps remained stable after about 1 hour.
3.510 Ghz----390----1.3175------1.272-------------1.240------------32 C----------52 C
3.600 Ghz----400----1.3575------1.312-------------1.272------------34 C----------58 C

Rojak's Bios Optimization Guide was once very useful, but the free version needs updating.

I have those ram formulas scribbled in my Epox 9NPA+ Ultra MB manual from a few years ago. I probably got them from one of Rojak's old Bios guides. They are for ddr. Are they still valid for ddr2?
I have, if I can read my writing, Tras = Tcl + Trcd + 2 and Trc = Tras + Trp

Q6600 GO stepping
Abit IP35-E
Geforce 7600 GT
4 x 1 GB Crucial Ballistix PC6400 DDR2-800
Vista Ultimate 64
2 x Maxtor 300 GB SATA HDs
Samsung SH-S203B SATA DVD Burner
Corsair 620W PSU
Cooler Master Hyper TX2 HS/fan
Antec 900 case

I think I had made an assumption that may not be true. The assumption was this: IF my DDR2-1000 Balli-sticks had an SPD/EPP default of 4,4,4,12 @ 800 Mhz, and the DDR2-800s had the same, the sticks would behave the same way (according to that review I cited -- written about the DDR2-1000's.) Like you, I'm building another machine with spare parts from my over-enthusiastic purchases for my Chrome-Lightning-Quad-WOPR build, and I had two sets of Tracers purchased as "NewEgg LanFest Crucials." These had the same model code as the DDR2-800 Tracers. I attempted to run them at known settings (3,3,3,6) I'd experienced for the DDR2-1000's, 1:1, FSB = 1,333 and DDR2=667.

I got a failure right away with MEMTEST86+ 1.70.

I think -- I speculate -- that settings that work on a single pair of sticks might have to be loosened for two pairs -- "proposition #1." #2 -- you will obviously need to run command-rate 2T with four sticks socketed. #3 -- if you pushed the voltage to the recommended maximum of 2.2V with two sticks, you may be s***-outta-luck with four unless you want to risk damaging them by over-volting.

The guide I read -- I can post the text of it below, says tRAS = tCL + tRCD for a tight tRAS setting. It doesn't add an integer of 2. This may result from a departure from DDR1 logic, and may have something to do with DDR2 "additive latency" -- which gives extra wiggle-room to a tCL setting (if I recall the proper latency -- properly.)

But what-EVER basic timings you use, you should be able to set tRC to either tRP+tRAS, or to tRP+tRAS + 1. That is, if you push a latency set to its limit by raising the FSB, you may have to add one to tRC.

Now -- on the matter of even being able to SET tRC -- I'm surprised it's not in the Intel BIOS, and for that, I feel bad for you. There've been all sorts of curses uttered about the 680i, most recently, about Yorkfield compatibility. Earlier, it was "FSB holes." Before that, mistakes in reference design excluding my ASUS board, another ASUS board and those by manufacturers allowed to deviate from the reference design. Also, I'm wondering if this guide wasn't written for the 680i chipset -- here . . . . just a minute:

Ram timing guide

As you can imagine, this has taken a lot of testing. 40-something benchmarks actually [ ] On to the point..

Each chipset (680i/975/965) acts differently to how timings are applied.
Some of you are probably familiar with how DDR1 ram acted on timings - DDR2 acts a bit differently and some timings are less important than what they used to be.

The EVGA 680i SLI board has an entire bios section dedicated to ram timings. So why not do some tweaking.
The guide follows the bios order, skipping Command Per Clock which is saved for last.

[photo of BIOS screen]

I've tested all timings one by one. Sisoft Sandra 2007 was used for benchmarking. All the first benchmark results were discarded since they tend to fluctuate.

My ram specs:
2x1gb Corsair PC2-8500C5 (D9)
Unlinked to 800mhz @ 2,175v
In blue DIMMs, running dual chan.
Base timings used: 5-4-4-12-(2T) / 3-23-5-9-(7,8)
Base Sisoft score: Int: ~5580 / Float: ~5570


tCL:
Large influence on stability / Medium influence on bandwidth
From CAS 5 to 4 results change ~5-10mb/s. The same change will most likely be seen when going to CAS 3.
This timing is widely seen as most important (Command rate disregarded).
Recommendation: 4 for normal usage, 5 when oc'ing. Tweaked: 3.


tRCD:
Medium influence on stability / Large influence on bandwidth
tRCD going from 4 to 3 gives ~15mb/s. From 5 to 4 also yields 10-15mb/s.
This timing is considered second important after CAS, but actually it's more important on 680i/DDR2.
Recommendation: 4 for oc/normal usage. 5 if you want to push mhz. Tweaked: 3


tRP:
Medium/small influence on stability / Small influence on bandwidth
Results vary close to nothing when changing from 3 to 4 to 5.
Still this timing needs to finish its cycle before a new one starts, so dont set it higher than 5.
Recommendation: 4 for oc/normal usage. 5 if you want to push mhz. Tweaked: 3


tRAS:
Small influence on stability / Small influence on bandwidth
tRAS seems to act differently on integer/float results. Integer, going from 15 to 10 changes by ~5mb/s. Float doesnt change.
tRAS is an "end-timing", so dont go to high. And not lower than what tCL+tRCD equals.
Recommendation: 12 for oc/normal usage. 15 if you want to push mhz. Tweaked: 8


tRRD:
Small influence on stability / Small influence on bandwidth
tRRD of 2 didnt change the results. Nor did a tRRD of 4. This is a delay-timing so a too low value may result in recalculation.
Recommendation: Auto for oc/normal usage. 4 if you want to push mhz. Tweaked: 2


tRC:
Medium influence on stability / Large influence on bandwidth
This timing is quite surprising. Going from 30 to 21 gave ~90mb/s. From 23 to 21 gave ~15-20mb/s.
tRC is last timing before ram burst (data transfer).
Dont set too high. And tRC should be greater than tRAS + tRP or you might get corruption.
Recommendation: 21 for normal usage. 30 if you want to push mhz. Tweaked: 15


tWR:
Small influence on stability / Small influence on bandwidth
Small change from 6 to 3. Setting timing too low will cause ram to fail switching to "read mode".
Recommendation: Auto for oc/normal usage. 6 if you want to push mhz. Tweaked: 3


tWTR:
Large influence on stability / Small influence on bandwidth
From 10 to 8 didnt change results. 6 would lock up the system. This timing gives no bonus but affects stability a lot. Use with care.
Recommendation: Auto for oc/normal usage. 10 if you want to push mhz. Tweaked: 8(7)

tREF:
Small influence on stability / Small influence on bandwidth
Changing to 3,9us didnt show improvements in benchmark. It also didnt seem to affect stability. tREF was important with DDR1.
Recommendation: Auto for oc/normal usage. 7,8us if you want to push mhz. Tweaked: 3,9us


Command Rate:
Settings are 2T/1T. You probably already know a lot about this timing.
The 680i struggles running 1T above 800mhz. So do the ram - atleast 2,2v are needed.
This timing gives a great boost to bandwidth, but is fairly hard to attain.
I wont recommend any setting regarding this timing. You need to find what mhz you get with 1T, then find mhz with 2T, then compare benchmarks.


Post words:
The tRC and tRCD are two timings to take notice of. They yield good results compared to how they affect stability.
CAS isnt as important as in the DDR1 days. You might even say timings in generel arent as important as with DDR1.

To read more on the technical aspect of DDR2 go here:
http://www.digit-life.com/articles2/...ddr2-rmma.html

If you feel like messing with timings from Windows, try this tool:
http://peecee.dk/uploads/0307/memset-3.2.zip
Note: CAS(tCL) timing cannot be changed.

Feel free to add/correct me if you have anything..

Happy tweaking!

 

[BonzaiDuck]

Anyway, if you get "good results" with a loosened tCL/CAS, what? -- 5? Then shine it on. Focus your attention on tightening tRCD, which may have an even more significant impact on bandwidth.

The last two "basic" timings would logically follow. I'm wondering if your chipset doesn't allow for automatic adjustment of tRC, since there's no specific setting for it? I'd look for "Turbo" or enhanced latency items on that BIOS page, and watch the part of the BIOS screen that provides those [traditionally sparse] explanations.

 

[brencat]

Many thanks for that guide Bonzai. I'm currently sitting at 4-4-4-8 2T (DDR 812) @ 2.05v right now and quite happy. System is 9hrs 45 mins Orthos blend stable -- just stopped it.

This weekend I also tried 3-3-3-9 and 3-3-3-6 2T @ 1:1 (DDR 650) with 2.1v. Everything tested fine and was Orthos stable but the performance was nothing to write home about given the 2T command rate. SP1M was over 20 sec in both cases.

Also tried 4-4-3-9 which I was initially excited about given it was 10hrs memtested and no errors. However, it failed Orthos in < 10 mins, and again despite additional voltage bumps.

4-3-4-8 was also a no go. Errored immediately in memtest. Gave it 2.2v, +3 MCH, and still did not like it.

I have 1 test left to try and that is 5-4-4-12 @ 1:1.5 (DDR 976), and if that works it will be between that and my current 4-4-4-8 @ 1:1.25. I'm somewhat skeptical given that I failed 5-4-4-9 a few days ago. Anyway, after that I plan to finally delve into my stack of games hard -- particularly Crysis, COD4, and COH. My friends can't believe I built my PC over a week and a half ago and still haven't loaded a single game yet. But they also don't understand the whole overclocking hobby and the patience needed with testing & tweaking.

All the best, B.

 

[MadScientist]

Originally posted by: BonzaiDuck
I think -- I speculate -- that settings that work on a single pair of sticks might have to be loosened for two pairs -- "proposition #1." #2 -- you will obviously need to run command-rate 2T with four sticks socketed. #3 -- if you pushed the voltage to the recommended maximum of 2.2V with two sticks, you may be s***-outta-luck with four unless you want to risk damaging them by over-volting.

I think all 3 of your propositions are correct. Even though the Ballistix are rated for 2.2V I'm going to try and keep them below 2.2V.

Since I read this AT article, had to dig to find it, back in 2003, I've always used Sissoft Sandra (buffered & unbuffered), and Super PI to benchmark my memory.
A quote from one of AT's recent DDR2 tests:
"The Buffered benchmark does not correlate well with real performance differences in games, so our memory bandwidth tests have always included an Unbuffered Sandra memory score. The Unbuffered result turns off the buffering schemes, and we have found the difference in Unbuffered results correlate well with real-world performance differences."

 

[MadScientist]

I have a few days off so have some time to work on my son's Christmas present and thought I'd resurrect this thread.
I have my ram currently running 1:1.25 on my Abit IP35-E but after reading Grasky's thread Memory bandwidth tests... any real differences (PC5300 vs. PC8888) and an Anandtech article on the new QX9650 in which they explain their oc methods, I may change my ram divider to 1:1 so that my memory runs synchronously with my FSB. Old ddr habits die hard though and I'm still not fully convinced that you don't get at least a small performance gain with an increase in mem frequency.
I have my Q6600 set at 3.303 Ghz (367 FSB x 9), at a 1:1.125 divider ram is at 918, 5-4-4-12-2T, and 2.1V, Memtest86+ and Prime95 stable. Anandtech still uses Sisoft Sandra and Super Pi as part of their memory benchmark software. DDR3 vs. DDR2 They did mention in the QX9650 article, referring to the X38 chipset though, that during the course of their testing they found the chipset able to drive two DIMM banks (2x1GB) at 400MHz FSB at a MCH default voltage (1.25V) while four banks (4x1GB) required a rather substantial increase to 1.45V. They also stated that as a general rule of thumb, cycle time (tRAS) should be set no lower than tRCD + tRP + 2 when using DDR2. I have not tried increasing the MCH voltage yet. That's next. It could be why my ram (4 x 1gb) Ballistix PC6400 is not Memtest86+ stable at it's rated 4-4-4-12, 800 mhz, 2.2V.

Here's some tests I ran using Sissoft Sandra XI SP2(unbuffered results) and Super PI 1.5 (5 run average). All configurations passed Memtest86+ and Prime95. Some ram settings that I tried passed Memtest86+ but did not pass Prime95 Blend.
CPU Speed(Ghz)---FSB----Divider----Vdimm-----Timings------Mem Freq--------Super PI(1M sec)----Super Pi(2M sec)----MemBandwidth (mb/sec unbuffered)
3.303----------------367-----1:1---------2.2-------3-3-3-8-2T------734-----------------16.00-----------------39.16----------------------------4718
3.303----------------367-----1:1---------2.1-------4-4-4-12-2T-----734-----------------15.84-----------------38.84----------------------------4598
3.303----------------367-----1:1.2-------2.1-------5-4-4-12-2T-----880-----------------15.96-----------------38.40----------------------------4957
3.303----------------367-----1:1.25------2.1-------5-4-4-12-2T---- 918-----------------15.93-----------------38.54----------------------------5156

3.150----------------350-----1:1---------2.1--------3-3-3-8-2T------700-----------------16.67-----------------40.53----------------------------4471
3.150----------------350-----1:1.2-------2.1--------5-4-4-12-2T-----840-----------------16.64-----------------40.54----------------------------4733
3.150----------------350-----1:1.5-------2.2--------5-5-5-15-2T----1050----------------16.60------------------39.85----------------------------5253

3.402----------------378-----1:1---------2.1--------4-4-4-12-2T-----756-----------------15.30------------------37.33---------------------------4704
3.402----------------378-----1:1.2-------2.1--------5-4-4-12-2T-----908-----------------15.22------------------36.98---------------------------5114
3.402----------------378-----1:1.25------2.1--------5-4-4-12-2T-----946-----------------15.19------------------36.49---------------------------5336

So how do you interpret these results. Quoting Anandtech, "The Unbuffered result turns off the buffering schemes, and we have found the difference in Unbuffered results correlate well with real-world performance differences." Graysky though presents a good case in his thread and concluded that higher memory bandwidth gives more or less no appreciable difference for real world applications. I found the standard deviation in the Super PI 5 runs ran as high as 0.5 sec on some runs, so Super PI showed no significant differences with higher mem freqs. As expected Super PI results with higher CPU speed were better.

I will have my son, a graphic designer, run 3D rendering benchmarks with Photoshop and Dream Weaver at these settings. For him, these will be real world application results.

Edit: I bumped the MCH (Memory Controller Hub) voltage up one notch from 1.25V to 1.29V and was finally able to get my 4 sticks of ram up to 832 mhz, Memtest86+ stable, at it's rated settings of 4-4-4-12T, 2.2V. I'll try raising the voltage one more notch and see what that yields.

 

[SerpentRoyal]

I see a larger change in 1M Super Pi as I move from 1:1 (388MHz/5-4-4-11-2T/16.234 sec) to 1:1.25 (485/5-4-4-111-2T/16.581 sec) memory divider. This amounts to about 105MHz gain in CPU core speed. Again, we're just looking at Super Pi V1.5 (1M and 32M runs).

The rig is IP35-E with E4300 running at 3.49GHz. According to SP, raising RAM speed from 388 to 485 yields a 2.8% gain in processing time...measurable but hardly noticeable under normal use. I also concur that running the RAMs at 388MHz with tighter timing will probably cut the gain to less than 2%.

 

[MadScientist]

Originally posted by: SerpentRoyal
I see a larger change in 1M Super Pi as I move from 1:1 (388MHz/5-4-4-11-2T/16.234 sec) to 1:1.25 (485/5-4-4-111-2T/16.581 sec) memory divider. This amounts to about 105MHz gain in CPU core speed. Again, we're just looking at Super Pi V1.5 (1M and 32M runs).

The rig is IP35-E with E4300 running at 3.49GHz. According to SP, raising RAM speed from 388 to 485 yields a 2.8% gain in processing time...measurable but hardly noticeable under normal use. I also concur that running the RAMs at 388MHz with tighter timing will probably cut the gain to less than 2%.

With the variations in Super PI results, as I had previously mentioned, its difficult to say if the difference between 16.234 and 16.581 is real. I saw differences between 5 runs at the same mem frequency of up to 0.5 sec. I don't know how many runs and averages at different mem frequencies you would have to make, 10, 100, 1000 before you are sure that a difference of less than 0.5 sec is real and significant.

 

[SerpentRoyal]

Originally posted by: MadScientist

Originally posted by: SerpentRoyal
I see a larger change in 1M Super Pi as I move from 1:1 (388MHz/5-4-4-11-2T/16.234 sec) to 1:1.25 (485/5-4-4-111-2T/16.581 sec) memory divider. This amounts to about 105MHz gain in CPU core speed. Again, we're just looking at Super Pi V1.5 (1M and 32M runs).

The rig is IP35-E with E4300 running at 3.49GHz. According to SP, raising RAM speed from 388 to 485 yields a 2.8% gain in processing time...measurable but hardly noticeable under normal use. I also concur that running the RAMs at 388MHz with tighter timing will probably cut the gain to less than 2%.

With the variations in Super PI results, as I had previously mentioned, its difficult to say if the difference between 16.234 and 16.581 is real. I saw differences between 5 runs at the same mem frequency of up to 0.5 sec. I don't know how many runs and averages at different mem frequencies you would have to make, 10, 100, 1000 before you are sure that a difference of less than 0.5 sec is real and significant.

I use the best possible time out of 100 runs. Wait 5 minutes after clean boot to allow windows to settle down before running the tests. This is actually an overkill since the best time is obtained only after about 20 tests. 1M deviation with my rig is less than +/-0.05 sec. It is imperative to terminate any application like LAN, AV, and FW running in the background.

32M Super Pi time can vary by +/- 2 seconds.

 

[MadScientist]

Originally posted by: SerpentRoyal
I use the best possible time out of 100 runs. Wait 5 minutes after clean boot to allow windows to settle down before running the tests. This is actually an overkill since the best time is obtained only after about 20 tests. 1M deviation with my rig is less than +/-0.05 sec. It is imperative to terminate any application like LAN, AV, and FW running in the background.
32M Super Pi time can vary by +/- 2 seconds.

In the interest of science, and I am I scientist, chemist by trade, I repeated one of the Super PI 1M tests (25 runs) with LAN, AV, and my FW off and with them on. There is a difference in repeatability. The difference between the highest and lowest reading with the apps off was 0.016 sec, with the apps on it jumped up to 0.251 sec.

Of course you have to realize these are synthetic benchmarks, and who normally runs their computer with LAN, AV, and their FW off.