Thunderbird and WPCUID cache info

[worldturning]

I'm using a 1ghz Thunderbird with an Abit KT7-Raid board. Can someone interpret this info from WCPUID?

[ WCPUID Ver.2.8 (c) 1996-2000 By H.Oda! ]
<< Cache Info. / Processor 1 >>

[L1 Instruction TLB]
2-Mbyte/4-Mbyte Pages, fully associative, 8 entries
4-Kbyte Pages, fully associative, 16 entries

[L1 Data TLB]
2-Mbyte/4-Mbyte Pages, 4-way set associative, 8 entries
4-Kbyte Pages, fully associative, 24 entries

[L1 Instruction cache]
64K byte cache size, 2-way set associative, 64 byte line size, 1 line par tag

[L1 Data cache]
64K byte cache size, 2-way set associative, 64 byte line size, 1 line par tag

[L2 cache]
256K byte cache size, 16-way set associative, 64 byte line size, 1 line par tag

[L2 Instruction/TLB]
2-Mbyte/4-Mbyte Pages, Off, 0 entries
4-Kbyte Pages, 4-way set associative, 256 entries

[L2 Data TLB]
2-Mbyte/4-Mbyte Pages, Off, 0 entries
4-Kbyte Pages, 4-way set associative, 256 entries

 

[paulip88]

I don't know why you would really like to know... but if you insist...

TLBs:
This is basically a cache that keeps track the mappings between the virtual addresses used by an application and the plysical address of the memory block in memory. More TLB would mean that you can handle more virtual address space in the cache simultaneously.

L1 Cache:
There are two L1 caches. One for instructions. This onestores all the assemby code instructions that the CPU is to run. The other is the data cache, which is usedto store data elements (like the stack).

L2 Cache:
This is a secondary chache that is used if the data is not in the first one.

Page Size:
The page size is how big the pages in memory are.

Associativity:
Caches operate by mapping certain physical addresses to certain certain spots in the cache. This means that a specific physical address can only go in one spot in the cache. This could be problematic if you have the case where you are using two addresses that are mapped to the same spot. The cache will never have the right info, and the cache wouldbe useless. This is where associativity comes in. Associativity reserves a set number of slots instead of one. So if two pages would map to the same area, it would be ok since there is space for more than one page in the area.

Fully associative means that the entire cache is open to any address. n-way associative means that each mapped area in the cache can have n pages stored in it.

Fully associative is only good for small caches since it makes lookup slower.

For even more detailed info, check out lectures 14-20 on the
15-213 Systems Level Programming web page.

 

[worldturning]

Thanks paulip88 for taking the time to answer. I was just looking for general information. I'll check out the link. Thanks again.