After reading a ton of technical data on PLXs website and a few articles on the subject (including Ian Cutress), Im still at a bit of a loss. I would like to confirm my observations.
IVB supports 16 PCIe 3.0 lanes directly from the CPU for a total bandwidth of 16 GB/s, theres nothing PLX can change about that. What their chip effectively does, as far as I can grasp, is manage available bandwidth in an intelligent way at the cost of latency which results in a small overhead (~2%). It increases lane count, but not actual bandwidth thus enabling tri-SLI on IVB. However, the bandwidth available to those three GPUs is still 16 GB/s, and not 32 GB/s.
Correct me if Im wrong on any count. Please, respond only if youre really informed.
IVB supports 16 PCIe 3.0 lanes directly from the CPU for a total bandwidth of 16 GB/s, theres nothing PLX can change about that. What their chip effectively does, as far as I can grasp, is manage available bandwidth in an intelligent way at the cost of latency which results in a small overhead (~2%). It increases lane count, but not actual bandwidth thus enabling tri-SLI on IVB. However, the bandwidth available to those three GPUs is still 16 GB/s, and not 32 GB/s.
Correct me if Im wrong on any count. Please, respond only if youre really informed.