- Aug 25, 2001
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I was just thinking about how Intel's current C2D Quad-cores are put together - two C2D dual-core dice in the same package, linked by their shared FSBs.
This configuration gives Intel huge manufacturing advantages. And it's all due to the "magic" of Intel's FSB designs, which allowed for cheap dual-socket SMP designs, and eventually dual-dualcore designs.
With Nahalem, this will all be at an end. But I wonder, how will Intel create Octo-core CPUs, with two native quad-core Nahalem chips? Especially if each quad-core is expecting it's own path to DRAM, with the integrated memory controller.
As far as I understand it, it's not easily possible to have two memory-controllers sharing the same DRAM. (Since the memory controller maintains a cache of things like open pages in DRAM and whatnot.)
So does this mean that we will wait longer for Octo-core CPUs, until Intel can create "native" Octo-cores, at some future generation?
I almost wonder if the loss of the FSB design is a step backwards for Intel, seeing as how their pre-fetcher in the C2D and the size of the L2 cache shows that they don't even need the IMC for performance reasons.
What do you all think?
This configuration gives Intel huge manufacturing advantages. And it's all due to the "magic" of Intel's FSB designs, which allowed for cheap dual-socket SMP designs, and eventually dual-dualcore designs.
With Nahalem, this will all be at an end. But I wonder, how will Intel create Octo-core CPUs, with two native quad-core Nahalem chips? Especially if each quad-core is expecting it's own path to DRAM, with the integrated memory controller.
As far as I understand it, it's not easily possible to have two memory-controllers sharing the same DRAM. (Since the memory controller maintains a cache of things like open pages in DRAM and whatnot.)
So does this mean that we will wait longer for Octo-core CPUs, until Intel can create "native" Octo-cores, at some future generation?
I almost wonder if the loss of the FSB design is a step backwards for Intel, seeing as how their pre-fetcher in the C2D and the size of the L2 cache shows that they don't even need the IMC for performance reasons.
What do you all think?