>According to OCinside is it possible to raise the multiplier above 12.5 >on the CPU with connecting the L10- bridges and the L4-bridges in >special ways.
>What would happen if I'd connect both L10-bridges?
>/steimm
Direct Answer:- "Russian Roulette"...you would be sending a signal to the most significant 8X bit in the Multiplier module that = Vcore/2, instead of Vcore (HI) or Ground (LO). So at the half-way point in the "range" the circuit designer cannot guarantee whether that signal level would be interpreted as a Logical HI or a Logical LO. It would be in the "indeterminate" range near the middle of the HI/LO signal range. Don't do it.
Advice:-You have 2 choices when you are thinking about changing the Multiplier by hard modding the various bridges and you do not fully understand how the logic or the circuits work.
1:- Go to sites with Tables of Settings vs bridges configuration/s and select your option/s, but do not try anything that is not listed in the Tables or shown in pictures...there are no other valid setting options.
2:- Go to a site like
http://www.beachlink.com/candjac/index.htm link to Final Decoding Palomino article which explains how the bridges are configured and how they are used to set/reset the Multiplier using the 5 individual Bit Values. If you can understand enabling and disabling Bit Values and remapping you will also understand that you never close or open both bridges in a "bridge pair"...one must always be open and the other closed...they act just like the common 3 pin/jumper sets in SS7 mobos...jumper on 1-2 OR 2-3, but never off both or on both. You will also be able to "diagnose" what went wrong (which bits/bridges) with your mod if/when you get unexpected results.
If you do not comprehend the material, then back to 1:- but don't try anything that's not shown.
BTW...we've seen many posts which seem to infer that the new L10 bridges on the Palominos are some sort of a special on/off switch. Not so, the L10 "bridge pair" either disables/LO or enables/HI a 5th 8X Bit Value used in determining what the final Multiplier will be. In this regard it is absolutely no different than the 4 L3/L4 "bridge pairs" which control the .5X, 1X, 2X, 4X, Bit Values of Palominos and the 4 bit Duron/Tbird chips. So would hope to see L10 bridges referred to only in that Bit Value sense.