As I said, I know how this rumor first started. And Sandra's reporting didn't do much to help this 
I think the FIRST well profiled mistake, was Andy Drake (of BXboards.com), reviewing the BH6 1.0, and mentioning that it had a 1/4 divider at 133 FSB. But in the SAME ARTICLE, he said that he had to reduce the PIO modes of the HD's to 3, in order to boot into windows.
Now, WHY THE HECK would you need to do that, if the PCI divider is /4, = 33 mhz?? Don't you guys remember back during the Socket 7 days, overclocking those MMX chips to 233 mhz +, or those AMD/Cyrix chips? Some of those cpu's were multiplier unlocked (my 166 MMX was unlocked but the locked ones required you to increase the FSB? And those boards didnt have 100 FSB yet.
There were posts all over about HD corruption at 83 mhz FSB (41 mhz PCI ), unless the PIO modes on the hd's were reduced.
Especially with cyrix chips, which, I believe, used either 75 or 83 mhz FSB by default.
So here is Andy Drake, having the SAME problem getting 133 FSB to work, then having to reduce PIO, and then claiming in the same article that the 1/4 divider is supported. Only a blind sheep would not smell a rat here.
To sum it up...
the PCI divider is NOT controlled directly by the BX chipset. It's controlled by the clock generator chip that is used on the motherboard. (the PLL IC). The BH6 1.0x boards used a IC works w124x clock generator, which supports 8 FSB speeds, with a divider of /2 and /3 only. A BIOS can not give a divider that a piece of hardware can't support.
The AGP divider is hardwired into ALL BX boards, not the PCI divider. (but don't quote me on this....i don't know if a newer 'revision' of the BX was necessary for proper implentation of the newer PLL IC's). Now, I'm also aware of those japanese Turbo PLL mods, where people were running > 150 FSB on BH6 1.0's (with proper dividers, etc), although obviously such a thing would require SoftFSB along with the PLL hacks, but again that's getting way off topic.
The 1.1x boards (as well as that famous Soyo board 6BA-III, that came out at about the same time), both used the W196x clock generator, which provided a /3 or /4 divider (you can choose) at 124 FSB, and /4 at anything higher, and there were a total of 30 UNIQUE FSB speeds. There were 32, but two of them were Spread Spectrum duplicates of the other ones).
I hope this clears up any confusion. Now we can stop having people flashing 1.1 bioses on 1.0x boards, or claiming a nonexistant PCI divider because of a buggy Sandra, or a flawed review.
I think the FIRST well profiled mistake, was Andy Drake (of BXboards.com), reviewing the BH6 1.0, and mentioning that it had a 1/4 divider at 133 FSB. But in the SAME ARTICLE, he said that he had to reduce the PIO modes of the HD's to 3, in order to boot into windows.
Now, WHY THE HECK would you need to do that, if the PCI divider is /4, = 33 mhz?? Don't you guys remember back during the Socket 7 days, overclocking those MMX chips to 233 mhz +, or those AMD/Cyrix chips? Some of those cpu's were multiplier unlocked (my 166 MMX was unlocked
but the locked ones required you to increase the FSB? And those boards didnt have 100 FSB yet. There were posts all over about HD corruption at 83 mhz FSB (41 mhz PCI ), unless the PIO modes on the hd's were reduced.
Especially with cyrix chips, which, I believe, used either 75 or 83 mhz FSB by default.
So here is Andy Drake, having the SAME problem getting 133 FSB to work, then having to reduce PIO, and then claiming in the same article that the 1/4 divider is supported. Only a blind sheep would not smell a rat here.
To sum it up...
the PCI divider is NOT controlled directly by the BX chipset. It's controlled by the clock generator chip that is used on the motherboard. (the PLL IC). The BH6 1.0x boards used a IC works w124x clock generator, which supports 8 FSB speeds, with a divider of /2 and /3 only. A BIOS can not give a divider that a piece of hardware can't support.
The AGP divider is hardwired into ALL BX boards, not the PCI divider. (but don't quote me on this....i don't know if a newer 'revision' of the BX was necessary for proper implentation of the newer PLL IC's). Now, I'm also aware of those japanese Turbo PLL mods, where people were running > 150 FSB on BH6 1.0's (with proper dividers, etc), although obviously such a thing would require SoftFSB along with the PLL hacks, but again that's getting way off topic.
The 1.1x boards (as well as that famous Soyo board 6BA-III, that came out at about the same time), both used the W196x clock generator, which provided a /3 or /4 divider (you can choose) at 124 FSB, and /4 at anything higher, and there were a total of 30 UNIQUE FSB speeds. There were 32, but two of them were Spread Spectrum duplicates of the other ones).
I hope this clears up any confusion. Now we can stop having people flashing 1.1 bioses on 1.0x boards, or claiming a nonexistant PCI divider because of a buggy Sandra, or a flawed review.
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