Originally posted by: LokutusofBorg
If you don't have RAM in the computer you'll get beep codes (how can you say it doesn't need it but it won't complete without it? /boggle).
POST consists of numerous individual tests and sub-routines that are executed by the CPU. Without a CPU, there will never be any POST. Here is a mile-high overview of power-on for standard x86 architecture:
After the CPU receives the correct reset signal and power, it starts itself in x86 real mode and will automatically access its reset vector. The reset vector is a default physical address containing the first instruction executed by the CPU. For all x86 processors in the past 10+ years, this address is 0xFFFFFFF0, which is mapped to BIOS ROM by the core logic. This address in BIOS ROM contains a 'jump' instruction to another location mapped to BIOS ROM, which contains the starting point of the actual BIOS bootstrap routine.
The bootstrap routine contains instructions required for early bring-up of the core logic, CPU, TLB, FPU, MSRs, MTTRs, interrupt controller, among other things. The DRAM controller is one of the last things to be initialized because you need to bring-up other things first. e.g.
Since DRAM initialization is one of the more likely points of failure during POST, it would be good to have debug output capability via serial port
before DRAM initialization. The serial port is almost always provided by the Super I/O chip connected via the Southbridge LPC interface. Therefore, in order to get a serial port working, you need to bring-up some of your Southbridge, too.
Not having those other things will cause POST to halt at some point. Without a CPU, you will never get to any POST. The system will be 100% non-responsive at any level.