Technical: What is a 'cache line'?

[xtreme2k]

I find out a P3 has a cache line size of 32byte and P4 has a line size of 128byte

What is a 'cache line' and what is a 'cache line size'?

I havent seen it mentioned in many articles

 

[Mday]

look up the cache differences between the fcpga p3 and fcpga celeron other than size.

 

[Noriaki]

When you read/write data from/to main memory you read it in lines. It's like the smallest exchangeable unit of cache.
So if you have a 256kB cache with 32B cache lines.
There are 8192 cache "slots" of 32B each.
So you can have 8192 areas of main memory cached.

Hope that made some sense...I'm not very good at explaining stuff sometimes...makes sense to me but I might as well be speaking Ancient High Elven to anyone else