Tech theory question - Can P4 use 266 DDR?

[grit621]

The P4 uses a 100MHz FSB, which is multiplied x4 => 400MHz, correct?

266MHz DDR is 133MHz that transmits on "both sides" of the signal, for an effective rate of 266MHz, correct?

It would seem that it would be difficult to apply 266MHz DDR to a chip that uses a 100x4MHz bus.

Is it possible that either:

1) The P4 Northwood/Brookdale will use a 133MHz x4 = 533MHz bus

2) The P4 Northwood/Brookdale will use SDR and DDR at 100MHz x4 = 400MHz bus (eg, 200MHz DDR)

If I'm wrong (easily possible), how will they work around this?

 

[Mookow]

I believe VIA's new P4 chipset is able to use PC2100. Maybe Wingznut PEZ can correct me if wrong

 

[Dually]

yes and Intel has a ddr chipset in works.

 

[splice]

hmmm... Another try for Intel at an async. bus, of course no MTHub this time 😉. It works the same way Athlons with a 200Mhz FSB can use PC133 133Mhz SDRAM.

 

[Wingznut]

Rumor has it that Via is making both a SDRAM and DDR RAM chipset. But I haven't heard of any official licensing deal between them and Intel.

 

[grit621]

But the k133 chipset uses SDRAM at 100MHz, thus underclocking it, correct?

Would this be the same case for the P4?

 

[Cutepunk]

At last fall's IDF, Intel stated that they won't be supporting PC2100 in Brookdale(i845), instead it will only support PC1600. Intel historically has favored synchronized bus, and PC2100 would make it asynchronous. But still, it would be logical to use PC2100 and set it at 2-2-2.

VIA favors asynchronized bus, so they will probably make one of those +33/-33 option in the bios. But I don't believe this will make much of a difference, because asynch bus has worse efficiency and stability compared to synchronized bus.

 

[Noriaki]

The Pentium4 is a 64bit 100Mhz QDR Bus.

How does Dual channel Rambus (32bit 400Mhz DDR Bus) match that any better than DDR (the total bandwidth numbers are the same, but it's not an equal bus). The i850 and i845 are both Asynchronous CPU (Front Side) and Memory Busses. They don't have to run at the same speed. And it's up to the north bridge to convert.

The Via KT133 does the same thing.
100Mhz DDR CPU bus and you can use a 133Mhz Memory Bus. And no it doesn't have to underclock the PC133 to 100. It can run them at different clocks. Your PC133 runs at 133Mhz, your CPU runs at 100.

Traditionally Memory and CPU busses were synchronous, but they don't have to be, and in newer chipsets they aren't usually (the AMD760 still is...but that's the only really new chipset I can think of that is).

 

[shathal]

One minor point - to make it clear again.

CPU FSB speed (the 400 MHz) are quite happy to run asynchronously from the MEMORY FSB-speed. Any half-decent chipset nowadays should be able to deal with this.

It's apples & oranges (in brief). You could make a 386 use RIMMs, in essence, if you could be bothered to do it.

P4 will work as happily with DDR as Athlon could work with RIMMs. It's not dependant on each other.

Right - hope this makes it a little cleared 🙂.

 

[grit621]

What about latency? I'm familiar with the CAS 2-2-2 numbers I see for SDR, and I know MOST DDR runs at CAS 2.5. What is RDRAM latency? How will that affect performance?