Tbred B 20x multiplier on ABIT KT7

[johncar]

Originally posted by: KF
>OK, maybe it it might work on the KT7. Wire Y3-X4 ,Y1-X2 and set 6.5 in the BIOS to get 21x.

I wired the CPU FID pins Y1 and Y3 to ground (VSS) and it did nothing. No 21x. No 13x, no 13.5x, and no 14x. All the multipliers that worked before still work the same.

I'll hazard a guess that ABIT has a circuit that substitutes its own FID, and that it is exactly the same as the multiplier it sets.

Believe you're right about FID's 4 bits being the same as 1st 4 Multiplier bits. See how the A7V handled this issue in the 3rd Duron/Tbird article at our site, You'll see that the Y3, Y1, W3, W1 pins are to the left of the 74F125 buffer, so the FID mod you just made would seem to get "locked out", and the low 4 bit FID signals to the Northbridge then come from the cross-connection from the Multiplier's 74F125 input to the FID's 74F125 output....lower than the 12.5X that should be there for Multipliers >12.5X, when 8X Bit Value is enabled.

But 15X boots even though its low 4 bits = 7X, less than spec'd 12.5X. Probably cause system timing "error/difference" just becomes "tolerable". As you can tell, we've been researching and playing this over with others. Looks like our Y3-Y1 mod is not going to work, at least in mobos that use designs similar to the A7V for auto-setting FID = to Multiplier. Sad thing is that that function "was needed" on Duron/Tbirds cause FID was set with bridges/circuits "separate from Multipliers. And in fact we heard of cases where Durons would not boot if only Multiplier bridges were modded/raised, the fix was to also raise the L6 FID bridges to equal or exceed the Multiplier's setting. Printed same in 2nd Duron article.

But since Palomino/Tbred which feed FID "from" Multiplier and seem to set 4 bit FID = 12.5X for 12.5X and up, those "legacy FID equalizing" circuits like the A7V's are "no longer needed", that's the sad thing. But probably kept there for backward compatibility to Duron/Tbird...and/or maybe the mobo designers are not aware of problems it's causing in 13X->14.5x range of Tbreds...at least most new mobos, as some do not seem to have this problem.

See edited Workarounds article, new Block diagram is better at showing the circuits "the way we'd like them to be" withut the 74F125s, but maybe we'll have to edit text further to reflect your failed experience. Hope to get your feedback on our comments and their plausiblity
John C.

 

[KF]

johncar;

I am baffled as to why the Northbridge itself would need to know the FID. I am reasonably sure that all the bus timing is identical regardless of the multiplier. Otherwise they'd have different timing diagrams in the processor books for different cases. The only thing that I ran across in AMD's processor books is that the processor gives the FID to the chipset so that the chipset knows what SIP to send to the processor. SIP = Serial Initialization Packet. The SIP sounds like something that is sent to the processor only once, to "initialize" something or other, and I'd guess that is the clock and PLL on the processor. The way they have to do this is that the CPU clock locks (via a Phase Locked Loop) to a multiple of the FSB. I really think the processor doesn't boot because the CPU's clock is set to something invalid. Maybe it doesn't matter why. It still has to be corrected somehow.

AMD says info about SIPs is in "AMD Athlon and Duron System Bus Specification", order #21902, but I can't locate anything like this on AMDs site or anywhere else. Did you ever find such a thing? 21902 looks like one of those numbers AMD puts on their .pdf documents.
99.9% of the doc is bound to be irrelavent to the subject at hand, and maybe it's too esoteric and complex, but it would be nice to know what this is all about instead of guessing at everything. I really don't care about the packets and their protocol, or any of the bus specs. I'd like to know what they are sending. What is the BIG SECRET? It must not have to be all that exact, because after 12.5x it is always supposed to be the same, and yet it works sometimes although it apparently isn't.

 

[johncar]

KF,
We get the following from 25175.pdf. Model 8 Athlon, Section 9, Power Up Requirements, pages 45 and 46....the CPU timing diagram and the 8 listed 'requirements".

The CPU is transferred to the Clock Multiplier (PLL) at requirement #3, well before the FID[3:0] signals to Northbridge and SIP data back at #7 and #8. So FID has nothing to with the BP_FID/Multiplier signals to the PLL per se, but seems that they can affect system operation via effects on system timing via SIP data, when we see the following quote in #8.

The chipset samples the FID[3:0] signals in a chipset-specific manner from the processor and uses this information to determine the correct serial initialization packet (SIP). The chipset then sends the SIP information to the processor for configuration of the AMD Athlon system bus for the clock multiplier that determines the processor frequency indicated by the FID[3:0] code. End Quote

Believe this has to be interpreted as setting up something like "variable delay time-->variable wait states/clocks" for handshaking during transfers between CPU and Northbridge/system on the "bus". Makes sense to optimize performance, and since system has no sense of "real time", so must convert wait states/delays into "clocks", which vary in time as function of frequency/Multiplier. Only thing that doesn't make sense is "no variation after 12.5X"...available "tolerance", or not enough pins for a 5th FID bit.

But we do know the following:-
1) Some Duron/Tbird systems would not boot if they were oc'd by modding the L3/L4 bridges but not the L6 FID bridges. Then they'd boot if FIDs were reset to => L3/L4s setting. reported in our Duron article, believe 1st or 2nd one.

2) The 3rd article shows how Asus A7V got around the separation of FID and Multiplier bridge signal circuits, which works fine for the then 4 bit 12.5X max Multipliers, 1st 4 bits for both always equal....but not so for 13X and up...bingo, Tbreds have a timing problem if old mobos and some new mobos kept those "4 bit legacy Duron/Tbird signal matching circuits". Sad thing is, Tbreds "don't need" those circuits as we believe the absence of FID bridges means that those signals must be biased internally from Multiplier signals, then passed thru some logic which maxes them at 12.5X when the 5th bit is HI. Make sense???

3) Systems which won't boot 13X->14X do boot 15X. Believe that the 1st 4 bits = 7X must result in sufficient wait states so systems boot/run...must be some "tolerance" in SIP timing data so don't have to go all the way to 12.5X for success.

System software and configuration is not our area of experise. So
what do you think??
John C.

 

[johncar]

KF,
Re how to fix the problem.
Look at the 74F125 circuits in the A7V article as an example, then
also our block diagram in Workarounds article as it "should be"
for Tbreds with no Red circuits from bios in Auto mode, and only the
one Red circuit to L1s in user-defined mode.
Seems like the #5 and #6 switches (A7V circuits) would have to be set differently than as shown for oc'g mode, and some traces would have to be cut. And what if sws #5/#6 are now solid state, then more trace cutting. We see a very messy mod. Do you see anything easier?? Hopefully not all mobos have this legacy configuration.
John C.

 

[KF]

Thanks for the reference. I have that doc (two versions) so I read a little before and after it.

>... configuration of ... system bus for the clock multiplier....
A lot of verbiage, but the words "system bus" indicate that the system bus IS somehow different for different mutlipliers. Maybe "system bus" could include a clock signal -it is a pretty general term-, but since they say a lot about the CPU clock and the PLL before this reference, and not here, it seems like FID is NOT involved in setting the CPU clock. Waits or delays sounds likely. Support for this is that only the FID for multipliers below 7x produce "no boot", with two exceptions, 11x and 12x. Probably the exceptions 11x and 12x are just invalid in the new scheme of 5 bit multipliers, where the 5th bit is high and not low.

All the problem multipliers have the 4th bridge low. Only two multipliers with the 4th bit low do in fact work, the ones for 19 (11.5) and 20 (12.5). So any FID with FID3 high may be "good enough" to work (corresponding to multipliers 7 to 10.5.) Your solution with both FID3 and FID2 hi always produces a still higher FID in terms of the multiplier code (11 to 12.5), which should be better.


>Re how to fix the problem.
>Look at the 74F125 circuits in the A7V article as an example, .... We see a very messy mod. Do you see anything easier??

A mod that maintains compatibilty is unlikely. I think I'd have to butcher the ABIT to accomplish anything, and I'd have to wring out the circuit to find out what to do.

There is one interesting thing about the A7V diagram which could be convenient. You could close the switch #5 so that the 74F125 tri-state buffer passes the FID signals to the North bridge, and leave all the multiplier switches open. That would always give you the correct FID for TBBs. You couldn't set the multiplier with the switches without screwing up the FID too, so switch #6 would have to be open. But you could cut the traces (blue in your diagram) going from the first 74F125 to the second. Then you would be free to set the multiplier with the switches. (Seems like just cutting the one for the 4th bridge should work, according to theory, but you might not want to ground any of the outputs of the top IC, which is what you would do if any of the other multiplier switches were closed.)

Finding the correct pins on either 74F125 that go from one to the other should not be hard, because the traces also go to the switches. A continuity check with a multimeter should tell you. Then you have to determine where the traces branch to the switches and the North Bridge and cut the correct branch.

 

[johncar]

KF,
Don't need to quote your last post 'cause we're in total agreement on all issues now, even your comments on modding the A7V's Tri-state buffer circuits...what a pleasure.;-)

We didn't mention that 'cause it's so messy, and "what if" sws #5 and #6 are now solid state on your mobo...more trace cutting.

Best workaround would then be 5 HI/LO switched circuits on a separate samll PCB connected to the 5 sockets the L1s are connected to. Then user runs system in "Auto" mode where the Tri-state buffer circuits "should be disabled", switches 1--> 4 are open. Multipliers then changed via the switches on new PCB. We show such a 5 switched circuit in Tbred article with all required sockets defined. Just need to solder 6 wires to sockets, 5 connect to the 5 Bit Value signal busses thru closed L1s, the 6th connects to a Vcore = Vcc/HI source socket, the 7th connects to case ground for LO source. Have another look at this issue in Workarounds article, just edited based on your results, and also other correspondents. Link there to the 5 sw diagram. Let us know what you think of that, esp as it's also available for future upgrades. And connect leads thru a connector for use on another mobo.

Once again...what a pleasure...thanks.
John C.

 

[KF]

>we're in total agreement on all issues now

I finally figured out what you already knew.

> Link there to the 5 sw diagram. Let us know what you think of that.
Looks OK to me. This is for Tbreds only.

Those 10 resistors will make it a bit of work. If you have break-before-make switches you could get by without so many, but who knows what you are getting when you got these switches? The mod doesn't require you to figure out anything about the mobo traces, and you don't have to cut any. If your mobo (like mine) does not have an "auto" mode that floats the multiplier controls and passes the CPUs FID to the North bridge, it won't work.

It should be possible to identify the pins on the North Bridge that receive the FID, cut the traces, and set the FID code to 12.5 by connecting the highs and lows appropriately.

It is only accidental that my ABIT KT7 works in default mode, such as when reseting the CMOS. The multiplier gets set to 12.5 and the voltage to what the CPU bridges specify. So my CPU, which has the 5th bridge open, making the multiplier 20x instead of 12.5, has to boot to 2000MHz at default voltage, although it is only rated at 1467MHz. A large OC at default voltage. Fortunately It makes it , but it isn't stable. If the 5th bridge were closed, it would only have to boot at 1250MHz.

I must have never had to reset the CMOS after I closed the L1 bridges on my 800MHz Tbird. There is no way it would ever boot at 1250MHz. With ithe CPU locked, the speed would have been normal (800Mhz) and the FID 12.5. But CPUs apparently work fine if the FID is higher than the multiplier. That must mean the 12.5 FID is the most conservative setting, the one sure to work.

This is also evidence and confimation that the FID does not affect the clock. Otherwise it would not make sense to have the 12.5 FID the default for every CPU. At the time I bought the 800MHz, AMD CPUs were just barely making 1000MHz, let alone 1250.

If you operate the CPU at a multplier less than 12.5, but the same net clock, you probably are using a tighter timing and therefore getting better performance from that fact alone.

 

[Soulkeeper]

dang i missed a lot of action in this thread hehe

 

[johncar]

Comments preceded by ****
>we're in total agreement on all issues now
I finally figured out what you already knew.

**** What makes you think we were 100% sure....always need confirmation from others.;-)

> Link there to the 5 sw diagram. Let us know what you think of that.
Looks OK to me. This is for Tbreds only.

**** Switch only low 4 bits for Duron/Tbred, set L6s to 12.5X if mobo does not have the Tri-state buffer design. Some did not, had to raise FID L6s setting when Multiplier was raised, else no boot.

Those 10 resistors will make it a bit of work. If you have break-before-make switches you could get by without so many, but who knows what you are getting when you got these switches?

**** Link to the last GFD article. There see a neat solution in the pic of the "miniMAX". No switches, the resistors make the connections to Vcore or ground bussed sip socket strips. This then gets the ON-OFF-ON switching you're looking for....only 5 resistors max, none soldered, float the default bits that fit your setting.

The mod doesn't require you to figure out anything about the mobo traces, and you don't have to cut any. If your mobo (like mine) does not have an "auto" mode that floats the multiplier controls and passes the CPUs FID to the North bridge, it won't work.

**** Right.

It should be possible to identify the pins on the North Bridge that receive the FID, cut the traces, and set the FID code to 12.5 by connecting the highs and lows appropriately.

**** Right, but not for everybody, so that's why we didn't write it up.

It is only accidental that my ABIT KT7 works in default mode, such as when reseting the CMOS. The multiplier gets set to 12.5 and the voltage to what the CPU bridges specify. So my CPU, which has the 5th bridge open, making the multiplier 20x instead of 12.5, has to boot to 2000MHz at default voltage, although it is only rated at 1467MHz. A large OC at default voltage. Fortunately It makes it , but it isn't stable. If the 5th bridge were closed, it would only have to boot at 1250MHz.

I must have never had to reset the CMOS after I closed the L1 bridges on my 800MHz Tbird. There is no way it would ever boot at 1250MHz. With ithe CPU locked, the speed would have been normal (800Mhz) and the FID 12.5. But CPUs apparently work fine if the FID is higher than the multiplier. That must mean the 12.5 FID is the most conservative setting, the one sure to work.

**** Yes, Clocks delay = (Specified delay secs)*(Clocks/sec)
So the higher the Multiplier, frequency, Clocks/sec, the more Clocks delay. Puzzle is why variable to 12.5X, then constant. Suggests lots of tolerance???

This is also evidence and confimation that the FID does not affect the clock. Otherwise it would not make sense to have the 12.5 FID the default for every CPU. At the time I bought the 800MHz, AMD CPUs were just barely making 1000MHz, let alone 1250.

If you operate the CPU at a multplier less than 12.5, but the same net clock, you probably are using a tighter timing and therefore getting better performance from that fact alone.

**** Sounds right. And sounds possible, since systems not booting 13X thru 14X but booting 15X, not needing a 12.5X FID setting, suggests there's tolerance in these timings..as we suggested above.
John C.

Soulkeeper,
Good to hear from you again. Any comments on these issues??

 

[johncar]

KF, Soulkeeper, et al,
Fresh news relevant to FID issue.
Helping a correspondent build and connect the external pcb with switches and resistors to wire to Multiplier sockets for Multiplier control of an Msi K7T Pro with no mobo provisions for changing the 7X default Multiplier of a Duron 700.
After solving construction problems, he was able to set 6.5X, 7X but all above returned only default 7X. So we "re-suggested" he close the top L6 FID bridge, ( only one open for 7X), which would reset the FID signals to Northbridge to 11X, (all 4 bits LO).

Then he was able to set and get 7.5X, 8X, and 8.5X...before he started to play with FSB settings and now no boot nada.
(Also using pencils which we deplore).

But the point here is to demonstrate/confirm the effect of FID setting relative to Multiplier setting....though we would have expected, (from other earlier reports), that 7.5X and up would "not" have booted at all, until the FID was => Multiplier. But....these issues do seem to be "mobo specific".

Interesting...yes???
John C.

 

[Vic]

johncar, I'm trying to get the 14x multi on my 2100+ TbredB and Epox 8K3A+ setup (KT333). Default multi is 13x, which works only when the BIOS is set to "Auto." Virtually all multi's above that to 18x are available, except 13.5x, 14x, and 14.5 (5.5, 6, and 6.5 in BIOS).
From the information on your (very informative) website, it appears that the 13x multi has L3 bridges of C--C--O--C--O and the 14x has C--O--O--C--O. From this I would assume that in order to get the 14x multi as "Auto," I would just need to cut (open) the 2nd bridge of the L3's. Is that correct? TIA.

 

[johncar]

Originally posted by: Vic
johncar, I'm trying to get the 14x multi on my 2100+ TbredB and Epox 8K3A+ setup (KT333). Default multi is 13x, which works only when the BIOS is set to "Auto." Virtually all multi's above that to 18x are available, except 13.5x, 14x, and 14.5 (5.5, 6, and 6.5 in BIOS).
From the information on your (very informative) website, it appears that the 13x multi has L3 bridges of C--C--O--C--O and the 14x has C--O--O--C--O. From this I would assume that in order to get the 14x multi as "Auto," I would just need to cut (open) the 2nd bridge of the L3's. Is that correct? TIA.

Yes, that's correct.

And as additional comment re the "no boot" issue for 13,5X, 14X, 14.5X(remaps to 21X)...see the Workarounds article at the section refering to same problem. Seems that if you're trying for them in "User-defined" Multiplier option your mobo may be subject to the FID over-ride problem from the bios, (the red circuit to FID signals going to Northbridge, which should be disabled in "Auto" mode). Do you agree??
Question though.... in user-defined, does bios show 14X for 14X, or does it show 6X, maybe 6X/14X for 14X? Just curious.
John C.

 

[KF]

>we would have expected, (from other earlier reports), that 7.5X and up would "not" have
> booted at all, until the FID was => Multiplier.

It was set to 7.5x and booted to 7x? It booted to a multiplier to which it was not set. How can it do that?


Just to make this clear, the ABIT KT7, unlike the ASUS A7V has no switches to set the multiplier. It is done from the BIOS only.

Curiousity got the better of good sense, and I have been tracing out the multiplier and FID circuitry on my ABIT KT7 for the last couple of days, starting from the CPU socket.

One problem: the chipset chips have no exposed solder pads, so you can't identify the FID pins, or any pins at all. The chips are surface-mounted, but there are no accessible pads; they are all underneath. I believe they call this BGA =Ball Grid Array. This means I can't confirm that FID even goes to the chipset. IAC, I can't find any traces that go to the chipset from the buffers that should send it there. The traces that might go there end at a resistor pack which has been left out out of the assembly. The traces could possibly continue to the chipset on the other side of the resistors that aren't there. Since this is a multilayer board, the traces could go to the chipset in one of the inside layers and I would never know it. My unconfirmed assumption is that they get there somehow.

The FID pins from the CPU socket go to some tri-state buffers (74244), whose outputs presumably go on to the FID pins of the chipset. On the output of these buffers, another set of tri-state outputs is connected. These are from a set of latches (74374), which are, no doubt, the way the KT7 sets the multiplier. Connected to this FID bus are some inputs to buffers, whose outputs go to the multiplier pins on the CPU. That means that whatever is put on the FID to the chipset also goes on to the multiplier. There is no way they can be different, which is as we guessed.

So there are two sets of signals that can go to the chipset FID. One from the CPU and one from the multiplier-setting circuitry (which is set from the BIOS). One or the other is enabled. The enable lines are driven from the opposite outputs of a filp--flop (7474), so that one of these is enabled, and the other is disabled. Therefore if the multiplier is soft-set to 21x, setting the FID at the CPU to something else can't fix the FID to the chipset.

I have been thinking that my mobo sets the multiplier to 12.5 in default mode, but I can see now that it could set the multiplier to the FID instead, and disable the multiplier circuitry. That means if the multiplier is "soft set" by the BIOS to something unbootable, you could get it boot to the FID multiplier instead even when the CPU is unlocked, by reseting the CMOS. It happens that this is a 20x for my TBB, which very high. But for my 800 Tbird, it would be 800, which is just right. I can check this by trying it on my unlocked 800.

 

[johncar]

Comments prefixed with ****

Originally posted by: KF[/i]
>we would have expected, >(from other earlier reports), that 7.5X and up would >"not" have >booted at all, until the FID was => Multiplier.

It was set to 7.5x and booted to 7x? It booted to a multiplier to which it was not set. How can it do that?

**** Ask the mobo designer.;-) Seriously, as we wrote, earlier reports were no boot on mismatch/FID lower. But why not some software that says "If FID < Multiplier the set Multiplier = FID".
The tester was credible, and did it for several settings. And as you wrote later, you seem to be coming to the same conclusion on your mobo.

****Scrubbing the rest of your post as we have no further comments, but do want to complement you on what seems to be a very thorough tracing job, albeit hard to follow from text, but knowing the A7V equivalent we get the general idea.
Maybe you could post a circuit diagram somewhere sometime later like we did for the A7V...love to have a copy.

Thanks for your time and supporting interest.
John C.

 

[johncar]

Guess what KF,
Checked records and the person whose system "locked" at 7X when he set 7.5X and up....had an MSI K7T Pro.

Did Abit and Msi use the same design..ie KT7, K7T ???
John C.

 

[KF]

I tried my unlocked Tbird 800 in the ABIT KT7, and it does boot to 800 in the default mode after a "no boot". That means it was using 8x as the multiplier and according to the circuit diagram it must be getting that from FID. There is no way to set it to this default mode from the BIOS though.

First I tried it with "1300 and above" set in the BIOS. Naturally it wouldn't boot. That's consistent with the multiplier being set to 12.5, which would be 1250MHz, way too high for the 800. Then I got it to boot in "default mode" by pressing INSERT while turning the power on. It came up 800.

As an aside: This processor is 2 1/2 years old. I used to have it in this very mobo. The best I ever got was 1G when it was new, and I tried real hard. Back then it would only boot at 1G when "the signs of the Zodiac were aligned just right. " Since I had it plugged in, just for the heck of it, I tried booting at higher MHz. I watched in awe as it booted at higher and higher frequencies. I got it up to 1090MHz. I got it to boot once at 1100, but only once. The knowledgeable experts say there is no such thing as "processor burn in", and I agree with their reasoning. OTOH, something happened. What?


>Did Abit and Msi use the same design..ie KT7, K7T

Lord only knows. I thought this MSI K7T mobo had no facitilities to set the multiplier and that's why you had the guy build a PCB with switches? If that is so, then the CPU was somehow using the FID instead of the multiplier bridges to set the multiplier to 7x instead of 7.5x.

 

[johncar]

Johncar & KF wrote,
>Did Abit and Msi use the same design..ie KT7, K7T

Lord only knows. I thought this MSI K7T mobo had no facitilities to set the multiplier and that's why you had the guy build a PCB with switches? If that is so, then the CPU was somehow using the FID instead of the multiplier bridges to set the multiplier to 7x instead of 7.5x. End quote.

Actually this person came to us "after" building the 5 sw pcb asking why it didn't work. We just checked thru all emails and he never mentions that the mobo has no such provisions, but we'd assume so, else why build the pcb. Anyway, he finally got the bugs out of the pcb and final report he was happy...after he also closed the L6s which we guessed might be limiting the oc to default 7X...and first time we had heard of FID "limiting", all earlier reports were that system would not boot if FID < Multiplier. Which gets us to your last sentence....

We'd guess the logic for the limiting would be on the mobo, since other similar Duro/Tbird reports came up "no boot". But that would mean there "are some such provisions" on that MSI mobo. Maybe he didn't recognize that there are?? He never mentioned any, so we just "assumed" none. Maybe he has similar to your Abit, plus some additional "limiting logic"?? As you say Lord only knows.
John C.

 

[KF]

Now that I have a diagram of my multiplier circuits, I discovered a possible way to get 21x (and it worked.)

My mobo sets the multiplier and simultaneously sets the FID. To get 21x I had to get around that. So I notice that there is a buffer IC to drive the multiplier pins on the CPU AFTER the IC that holds the multipler. Therefore I can put a wire in the CPU socket to force a multiplier pin low despite the fact my mobo is trying to set it high. So I did this with the 4th multiplier bit.

(The buffer IC can only pull the multiplier pin low. To get a high they use a pull-up resistor. So it won't damage the buffer IC if I short it to ground.)

So if I set the multiplier to 1111 (= 10.5x)in the BIOS, there is 10111 (=21x) at the CPU pins. 10.5x is a high enough FID that the CPU should boot, according what we already deduced.

(da-DAH...) So it boots up at 21x (2100 MHz). This confirms that the CPU is capable of 21x, and that FID is the source of the no boot.

Since the 5th bit is always 1 and now the 4th is always 0, there are eight possible combos, and I tried them all.

BIOS 10.5x = 1111 -> 10111 boots 21x
BIOS 10.0x = 1110 -> 10110 boots 14x
BIOS 9.5x = 1101 -> 10101 boots 13.5x
BIOS 9.0x = 1100 -> 10100 boots 13x
BIOS 8.5x = 1011 -> 10011 boots 20x
BIOS 8.0x = 1010 -> 10010 boots no
BIOS 7.5x = 1001 -> 10001 boots 19x
BIOS 7.0x = 1000 -> 10000 boots no

These are the only multipliers you can get with the mobo set up this way. This could be useful for people that need the multipliers 13, 13.5,14, or 21.