Sudden jump in power consumption of haswell

[Dufus]

Have you tried disabling IVR efficiency?

 

[futureishere]

Have you tried disabling IVR efficiency?

There is no option in my BIOS to disable IVR efficiency!

 

[Dufus]

You can do it via software. Maybe try XTU.

 

[futureishere]

You can do it via software. Maybe try XTU.

My Haswell machine doesn't have windows installed. Let me see if I can figure out a way to disable VR Efficiency mode in Ubuntu.

 

[Dufus]

You could use the msr-tools package or the UEFI shell before loading the OS.

ToggleEFF.zip an EFIwhich under UEFI will toggle your IVR efficiency.

 

[futureishere]

You could use the msr-tools package or the UEFI shell before loading the OS.

ToggleEFF.zip an EFIwhich under UEFI will toggle your IVR efficiency.

Thanks, apparently I hadn't looked hard enough last night. I was able to find the IVR settings in my BIOS. I tried out all three IVR efficiency settings: Auto, High performance and Balanced but it didn't make any difference. I am however not sure how changing these settings would affect the efficiency curve of the power cell.

 

[Dufus]

It will force IVR to always run in max power delivery capability mode.

http://download.intel.com/support/m...z87klt75k_overclocking_assistant_june2013.pdf

 

[know of fence]

Here's a bunch of press briefing slides about Haswell, on page 10 it shows how 1.8 V go into the FIVR and 12 different "V"s come out.

Searching I came across this presentation about integrated VR research. Although flipping through the slides I couldn't tell you if those VR's use PWM, induction, resistors or all of the above to adjust voltage. I can see in this particular case they used 20 power cells with 16 phases each, there are also some efficiency curves and mention of algorithms that are supposed to keep efficiency curves flat, switching phases perhaps like you suggested.

In hindsight it seems that there is no good reason cramming VRs "with efficiency in the low 80's" on an already dense and hot chip, unless there is also some reduced switching latency that perhaps saves power by quickly adjusting. But it seems they just wanted to save space and continue with further SoC integration.