Stretch a 90.3mm² @ 65nm design to 90.3mm² @ 45nm. The result?

[blyndy]

If a 65nm design was made with 45nm but keeping the 65nm die size, what would be the result of this extra manufacturing 'resolution' and precision?

Putting aside that the transition in process nodes is not a simple copy and paste, and the less profit per wafer, wouldn't the yield be increased?

E.g. A 65nm Core Duo (Yonah) with a die size of 90.3 mm² (according to Wikipedia). Put it onto a 45nm process and stretch the masks so the finished die has the same (90.3 mm²) size. The circuit traces would be much more accurate and robust, leading to the thought that the voltage/frequency could really be pushed up.

Or to take another approach get a 45nm design (e.g C2D Wolfdale, 107 mm², 6MB L2-Cache), lop off half of its ample cache and then stretch it back out to (roughly) 107 mm² (for reference the Core i7 die size is 263 mm²). I would definitely trade half the cache for a retail clock speed of 5-6Ghz.

Well that's just my imagination. I'm interested to know what the actual results would be. Higher efficiency? Lower Power? Hotter/cooler? Most importantly, the clocks: amazingly high?

 

[SickBeast]

You will need IDC to properly answer this.

I will say that AFAIK you cannot simply shrink a design to that extent due to a number of issues.

 

[yh125d]

At higher clock speeds, it will need that big cache even more

 

[Idontcare]

Originally posted by: blyndy
The circuit traces would be much more accurate and robust, leading to the thought that the voltage/frequency could really be pushed up.

While you can unintentionally have circuit traces that could limit a device's clockspeed, these are typically identified and eliminated in very early simulations and A0 silicon.

Generally what tends to limit the clockspeed of a chip is the switching speed of the transistors. However wire-delay (also called RC delay) would be a problem if you forced a diesize to be larger than needed as all the signals must travel that much farther between transistors.

It is this switching speed that is improved in new process nodes. Improved by making things smaller, closer together, and yes this does entail a certain degree of increasing the process control over process variability.

So if I were to take what I believe to be the spirit of your question, add in some basic device physics to guide the question into one which is technically feasible, then the answer is basically that yes you could do it but it would not be simple stretch though, it really would be a full re-layout to manage the capacitance and line delays, etc.

But so lets put all that aside and say "yeah yeah, so the smarties who do this for a living do it and they do it right...and we end up with a 65nm die sized penryn...does it clock faster just because the the added process control over process variability from 45nm development is used?"...the answer will most likely be no it will not clock any higher for this reason alone.

It will clock higher than a 65nm process equivalent because the transistors themselves have higher switching speeds being based on 45nm process tech but it would not clock as high as a 45nm diesize penryn because the wire-delay of 65nm diesize penryn would be worse than the 45nm diesize penryn.

Basically what it comes down to is that the reduced die-size is part of the reason the chip clocks higher, in addition to better control over process variability plus the obvious new technologies that are implemented in their own right (HK/MG for example).

 

[dmens]

Originally posted by: Idontcare
However wire-delay (also called RC delay) would be a problem if you forced a diesize to be larger than needed as all the signals must travel that much farther between transistors.

imho proper/aggressive pipelining can almost completely defeat the RC scaling problem even today. and EOL steppings tend to be gate limited, not wire limited with regards to speed.

so maybe with the large gates on a big penryn, it might just clock faster than a regular penryn, once the work is put in on the design side to optimize the layout. also consider that with the extra room, you can use wider wires to reduce resistance.

 

[pm]

imho proper/aggressive pipelining can almost completely defeat the RC scaling problem even today.

Yeah, at a cost to power.