Strained Si/Ge and the loss

[poorchap]

Silicon? Intel's push for strain-free fabs seems ok, but I've always been curious why the straining worked yet caused the thermal loss.

 

[TuxDave]

I'm a little lost on what you're asking. If you're asking why using strained silicon can reduce power on a processor then....

Strained silicon has less resistance in their channel since (in my mental picture), the silicon atoms are pulled apart leaving more room for electrons to pass through. As a result, given equal transistor sizes, the strained silicon will be able to push through more current. So now you have two options you can play with this. You can now start using smaller transistors which leads to smaller capactances which leads to lower power usage OR you can increasing some channel lengths or increase the threshold voltage to decrease leakager current. Either way, both reduce power.

Is Intel really moving away from strained silicon?

 

[f95toli]

Originally posted by: TuxDave

Strained silicon has less resistance in their channel since (in my mental picture), the silicon atoms are pulled apart leaving more room for electrons to pass through.

It is not that simple. I don't know much about strained Si but I have some knowledge about condensed matter in general. Many materials change their electronic properties significantly when strained (or under pressure), the reason is that the strain modified the phonon spectra which in turn direcly affects properties like thermal conductivity and indirectly the conductivity (electron-phonon scattering) and other elecronic properties (a nice example is the critical temperature of superconductors).

Hence, it is not as simple as there being "more space", it is much more complicated than that and I don't think there is a simple answer to the question.

 

[TuxDave]

Originally posted by: f95toli

Originally posted by: TuxDave

Strained silicon has less resistance in their channel since (in my mental picture), the silicon atoms are pulled apart leaving more room for electrons to pass through.

It is not that simple. I don't know much about strained Si but I have some knowledge about condensed matter in general. Many materials change their electronic properties significantly when strained (or under pressure), the reason is that the strain modified the phonon spectra which in turn direcly affects properties like thermal conductivity and indirectly the conductivity (electron-phonon scattering) and other elecronic properties (a nice example is the critical temperature of superconductors).

Hence, it is not as simple as there being "more space", it is much more complicated than that and I don't think there is a simple answer to the question.

Haha, I agree. I was never really good at device physics and so I had to visualize things in simple ways to remember how they worked. That's why I'm a circuit designer now. In my opinion it's infinitely easier than figuring out the difference between BSIM models and EKV device models... *gag*

But anyways, the bottom line is still the same. Given a transistor with better conductivity, you can use that to reduce power.

 

[poorchap]

I think that's what I'm trying to say. What got me thinking about it was this page of an article from THG that suggests strain contribute to current leakage loss and more thermal dissipation.

I would've thought the increase in conduction would help decrease loss.

If memory serves me right, the strain changes the band structure and the material becomes more "metallic". So it would seem getting rid of whatever it is sitting in the river of electrons would help.

 

[f95toli]

First of all: As I said above you can NOT think about "rivers of electrons", it is much more complicated than that. You MUST use quantum mechanics, semi-classical models do not work.

I did a quick INSPEC seach and found a review paper from 2003 (L. Collins, IEE Review 2003, pp. 46-49, 2003). This is the explanation used in that paper.

There are actually two effect.
*In unstrained Si the lowest energy level in the conduction band has sex discrete electron states. It only takes a small input of energy from e.g. a acoustic phonon for a electron to change its state. When the lattice is strained the symmetry of the system is broken, the lowest energy level of the conduction band is split, with two of the orignal six levels dropping to a lower energy level and the remaining four rising to a higher level.

This means that it is now much more difficult for electrons to be scattered between the lowest energy states by a phonon, because there are only two states to occupy.
The net effect is that the average distance an electron can travel before being scattered is increased.

*The second effect is that the effective mass of electrons in strained Si is lowered, leading to an increase in conductivity.


I hope that help. It is a pretty good article which is easy to read so if you have access to IEE you can look it up yourself.

 

[poorchap]

I *think* I understand, but it still doesn't explain the higher thermal dissipation in strained systems versus unstrained. Shouldn't the decrease in two energy levels and an increase in conduction suggest lower loss effects?

I think (only speculating here) the strain isn't perfect and there are manufacturing defects inherent in the processing steps. Maybe there is nonuniform straining such that some parts of the silicon remain at lower lattice spacings that introduce barriers. The electrons hit the barriers and have a smaller overall mean free path.

 

[TuxDave]

Maybe I have too much ADD and skipped over something, but in the article it seems to be comparing strained silicon vs SOI. Not strained silicon vs traditional bulk CMOS

"Intel keeps using its strained silicon technology rather than SOI (silicon on insulator) which is known to suffer less from current leakage."

 

[pm]

"Intel keeps using its strained silicon technology rather than SOI (silicon on insulator) which is known to suffer less from current leakage."

These are two separate things that can be used together. SOI is used to reduce some fringing capacitance and to reduce substrate leakage and can be used to improve FET packing density but at a cost of higher wafer costs, and anecdotely lower yield. Strained silicon is a method of using another material (germanium) to induce strain on the silicon within the conduction channel to improve carrier mobility in the channel. You can do strained silicon on SOI - in fact, I believe IBM has announced that it is doing this one it's next generation process technology.