The number of stages in a pipeline will have an adverse affect on a branch mispredict.
A mispredict will cause the entire pipeline to be flushed. Take a Pentium 4 for example. If an instruction has reached the 15th or so stage, and is found to be a mispredicted execution, then the 15 cycles the instruction has gone through has been wasted and new instruction needs to be executed, 15 cycles (at least) later than if it had been predicted correctly.
A shorter pipeline means that the misprediction penalty is a lot smaller.
Did you read that other post that I linked for you the other day?