Here's some info taken from Adrian Wong's "The Bios optimization guide 6.2:
SDRAM Bank Interleave
Options : 2-Bank, 4-Bank, Disabled
This feature enables you to set the interleave mode of the SDRAM interface.
Interleaving allows banks of SDRAM to alternate their refresh and access cycles. One
bank will undergo its refresh cycle while another is being accessed. This improves
performance of the SDRAM by masking the refresh time of each bank. A closer
examination of interleaving will reveal that since the refresh cycles of all the SDRAM
banks are staggered, this produces a kind of pipelining effect.
If there are 4 banks in the system, the CPU can ideally send one data request to
each of the SDRAM banks in consecutive clock cycles. This means in the first clock
cycle, the CPU will send an address to Bank 0 and then send the next address to
Bank 1 in the second clock cycle before sending the third and fourth addresses to
Banks 2 and 3 in the third and fourth clock cycles respectively. The sequence would
be something like this :-
1. CPU sends address #0 to Bank 0
2. CPU sends address #1 to Bank 1 and receives data #0 from Bank 0
3. CPU sends address #2 to Bank 2 and receives data #1 from Bank 1
4. CPU sends address #3 to Bank 3 and receives data #2 from Bank 2
5. CPU receives data #3 from Bank 3
As a result, the data from all four requests will arrive consecutively from the SDRAM
without any delay in between. But if interleaving was not enabled, the same 4-
address transaction would be roughly like this :-
1. SDRAM refreshes
2. CPU sends address #0 to SDRAM
3. CPU receives data #0 from SDRAM
4. SDRAM refreshes
5. CPU sends address #1 to SDRAM
6. CPU receives data #1 from SDRAM
7. SDRAM refreshes
8. CPU sends address #2 to SDRAM
9. CPU receives data #2 from SDRAM
10. SDRAM refreshes
11. CPU sends address #3 to SDRAM
12. CPU receives data #3 from SDRAM
As you can see, with interleaving, the first bank starts transferring data to the CPU in
the same cycle that the second bank receives an address from the CPU. Without
interleaving, the CPU would send the address to the SDRAM, receive the data
requested and then wait for the SDRAM to refresh before initiating the second data
transaction. That wastes a lot of clock cycles. That's why the SDRAM's bandwidth
increases with interleaving enabled.
However, bank interleaving only works if the addresses requested consecutively are
not in the same bank. If they are, then the data transactions behave as if the banks
were not interleaved. The CPU will have to wait till the first data transaction clears
and that SDRAM bank refreshes before it can send another address to that bank.
Each SDRAM DIMM consists of either 2 banks or 4 banks. 2-bank SDRAM DIMMs use
16Mbit SDRAM chips and are usually 32MB or less in size. 4-bank SDRAM DIMMs, on
the other hand, usually use 64Mbit SDRAM chips though the SDRAM density may be
up to 256Mbit per chip. All SDRAM DIMMs of at least 64MB in size or greater are 4-
banked in nature.
If you are using a single 2-bank SDRAM DIMM, set this feature to 2-Bank. But if you
are using two 2-bank SDRAM DIMMs, you can use the 4-Bank option as well. With 4-
bank SDRAM DIMMs, you can use either interleave options.
Naturally, 4-bank interleave is better than 2-bank interleave so if possible, set it to
4-Bank. Use 2-Bank only if you are using a single 2-bank SDRAM DIMM. Note,
however, that Award (now part of Phoenix Technologies) recommends that SDRAM
bank interleaving be disabled if 16Mbit SDRAM DIMMs are used.
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