A RISC processor has got a pipeline with k = 5 stages. On average 1/20 of the total instructions is a load or store and it requires an additional access to the memory. The memory accesses are optimized with a cache memory with an average hit rate of 85%, every miss in the cache causes a pipeline stall of one stage. Calculate the speed up factor neglecting the pipeline loading phase thus assuming that the number of instructions tend to infinity.
The speed up factor is the ratio between the time required without a pipeline and the time with a pipeline.
Usually if tk is the stage period, k the number of stages and N the instruction number the speed up factor is:
.............N * k * tk..............N* k
sk = ________________ = ____________
..........k * tk + (N - 1) tk .... k + N - 1
With our data the answer should be
......... N * k * tk + (1/40) * N*tk.......................... k+ (1/40)
sk = __________________________________= ________________________= 4.8845
.....N*tk + (1/40)*N*tk + (1/40)* 0.15 * tk..........1+ (1/40) + (1/40)* 0.15
But the right answer is 4.466956 , so where is my mistake?
The speed up factor is the ratio between the time required without a pipeline and the time with a pipeline.
Usually if tk is the stage period, k the number of stages and N the instruction number the speed up factor is:
.............N * k * tk..............N* k
sk = ________________ = ____________
..........k * tk + (N - 1) tk .... k + N - 1
With our data the answer should be
......... N * k * tk + (1/40) * N*tk.......................... k+ (1/40)
sk = __________________________________= ________________________= 4.8845
.....N*tk + (1/40)*N*tk + (1/40)* 0.15 * tk..........1+ (1/40) + (1/40)* 0.15
But the right answer is 4.466956 , so where is my mistake?