Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[yuri69]

A TSMC 5nm Zen-ish die was reportedly taped out in mid-2020. So yea, AMD most probably have a some sort of Zen 4 ES.

Zen 4 shouldn't be held back by the Zen 2's IOD, also the shift to 5nm brings a space for creativity. So yea, Zen 4 shouldn't be a mere "tick". However, the "5GHz all-core thanks to 5nm" claim is a pure BS.

Genoa being 29% faster than Milan at the same clocks might be true if the tested workloads benefit from memory b/w - new IOD + DDR5 should provide plenty. The general purpose averaging metric aka IPC gain will be likely notably lower.

The guy is right about the consoles (and big GPUs) eating the 7nm wafers, so using any different process should mitigate that. But there is still Apple with their wild ramp.

---

TBH we don't know even the high-level planning behind Zen 4 and Zen 5. Truth is, the Zen architecture is quite conservative. So we might see a bit more radical departure from those. Zen 2 brought a very radical change using the separated IO approach but the core IP itself was still a straight evolution.

That revolutionary change might come with Zen 4, Zen 5 or even a non-zen architecture.

 

[Panino Manino]

Whether you believe it or not. When AMD introduced Ryzen they had a roadmap up to Zen 4. Anything beyond is new architecture beyond the original Ryzen platform.

That it's new and different I know.
That it'll be this much better however? I'm doubtful, that's what I mean.
The troubles ended? These chipmakers will keep having success stories indefinitely, without bumps on the road? Isn't wishful thinking? Though, this doesn't mean that AMD will be the one to hit the bump and fall, again.

 

[moinmoin]

AMD just managed significant gains on the same node, with just changes within the core. A switch to a superior node is usually the easy way to achieve further gains. Doubting a repeat of Zen 3 (likely with Zen 5) makes somewhat sense, doubting Zen 4 (which will profit of the improvements of N5 over N7 even before any changes to the cores, uncore and platform) less so.

 

[zir_blazer]

A TSMC 5nm Zen-ish die was reportedly taped out in mid-2020. So yea, AMD most probably have a some sort of Zen 4 ES.

Zen 4 shouldn't be held back by the Zen 2's IOD, also the shift to 5nm brings a space for creativity. So yea, Zen 4 shouldn't be a mere "tick". However, the "5GHz all-core thanks to 5nm" claim is a pure BS.

The amazing thing is that having the IMC on the IOD instead of the CCD is that if the next Socket design is behind schedule or DDR5 slips, they can still mix and match the current DDR4 IOD with a potential Zen 4 CCD and keep AM4 going. We're used than DDR generation switches provides around the same performance for two or three times the price due to new, more expensive Motherboards and Memory Modules. It may be worth to see if AMD has a Plan B for that.
I would intentionally leave Intel alone the weight of being an early adopter of a new RAM generation and having to push it, like they usually do. Imagine if DDR5 is stupidly expensive or has availability issues and it directly impacts Processor sales because you can't finish a full build. At least you can currently use an older Video Card in a new build. Good thing is that Intel seems to be including two DDR generations on their IMCs, Haswell-E and Skylake supported both DDR3 and 4, so if DDR5 launch is lackluster a new platform may still be viable if they bothered to include DDR4 support.

 

[DrMrLordX]

The case for N6 is even more complex due to its extensive use of scarce EUV machines that should be better used for N5.

Of all of TSMC's EUV nodes, I had thought N6 made the least use of EUV equipment. It was also supposed to be a cheaper alternative for those wanting to stay on N7's design rules (as opposed to using N7P->N5->N5P).

 

[moinmoin]

Of all of TSMC's EUV nodes, I had thought N6 made the least use of EUV equipment. It was also supposed to be a cheaper alternative for those wanting to stay on N7's design rules (as opposed to using N7P->N5->N5P).

The original plan was N7 being completely DUV, N7+ having 4 EUV layer, and N6 having 5 EUV layers. For comparison N5 uses 14 EUV layers. So going by the amount of layers N6 is about a third of N5, which could still be a problem for EUV availability for N5 if indeed most N7 customers move capacity usage to N6 sooner than later. I'm sure for TSMC and many of its customers cutting edge N5 has priority over a mere long term optimization that is N6.

 

[yuri69]

The amazing thing is that having the IMC on the IOD instead of the CCD is that if the next Socket design is behind schedule or DDR5 slips, they can still mix and match the current DDR4 IOD with a potential Zen 4 CCD and keep AM4 going.

There is a problem of interface changes. The DDR5 IOD will surely use an updated version of IF. It would require to make the Zen 4 CCD interface compatible with both old and new IF. This keeping this kind of compatibility *might* be costly.

Besides, Zen 4 server really needs all that DDR5 bw if the Genoa tops at 96c.

 

[zir_blazer]

There is a problem of interface changes. The DDR5 IOD will surely use an updated version of IF. It would require to make the Zen 4 CCD interface compatible with both old and new IF. This keeping this kind of compatibility *might* be costly.

Besides, Zen 4 server really needs all that DDR5 bw if the Genoa tops at 96c.

EPYC/TR already uses a different IOD, so execution of those plans are totally different to AM4 side. Besides, Server people are more likely to pay the RAM premium if it brings any tangible benefit (Usually density), consumers are the ones quite price sensitive.

AMD had hidden tricks in the IOD IF. Consider than on Matisse you could have two dies with 4 CCX and each had its own independent path to the IOD, because while there were 2 CCX per die, they couldn't directly talk between them at all and had to go back and forth from the IOD. Vermeer has 2 CCX, so a single patch between each die and the IOD, but the IF links should have been teamed to have twice the width (Sort of like PCIe Lanes when you bifurcate 16x to 8x/8x, but the other way around). I don't recall anyone mentioning than the IOD could join two IF links, so there should be a lot of hidden features in silicon.
Also, mismatching generations are not new at all. I'm almost sure that there were K8/K10 generations with a notorious HyperTransport mismatch, like running a 2010 Athlon II X6 Thuban on an AM2 Motherboard. So if they make IF improvements, it will be a backwards compatible superset.

 

[Kedas]

Any chance that Zen4 is a 12 core die?
Sounds like a logical change to me, by that time 8 cores will be the minimum people buy, and if not you can still buy the DDR4 platform for low end.
6 cores on DDR5 doesn't sound right anyway now.
It would also llimit the changes needed to make an 96 cores Epyc.

Then CPU 6950X or 7950X will be 24 Cores...

or did AMD already say 8 cores per die for Zen4?

 

[Thunder 57]

Any chance that Zen4 is a 12 core die?
Sounds like a logical change to me, by that time 8 cores will be the minimum people buy, and if not you can still buy the DDR4 platform for low end.
6 cores on DDR5 doesn't sound right anyway now.
It would also llimit the changes needed to make an 96 cores Epyc.

Then CPU 6950X or 7950X will be 24 Cores...

or did AMD already say 8 cores per die for Zen4?

Not a chance. They just redesigned the CCX/CCD.

 

[Ajay]

Not a chance. They just redesigned the CCX/CCD.

I agree, given the boost in 'IPC’ AMD is supposedly shooting, for there is a lot of work to be on the front end, execution units/pipelines, various buffers, retire and maybe more cache if the pressure on DRAM increases too much (Which I think is likely).

 

[Timorous]

Not a chance. They just redesigned the CCX/CCD.

Agreed. If AMD want more than 16 cores on the desktop they could always make sure that a 3 + io config fits to get your 24 cores. Not sure that is needed though but they could design it that way for zen 5 perhaps. Although if it is Alder lake vs Zen 4 for a while I could imagine AMD going why have 24 threads when you can have 24 cores.

 

[moinmoin]

Since Zen 4 will introduce new platforms the definition of e.g. AM5 may allow for more flexibility, like a bigger package that can hold more chiplets etc. so anything is possible really.

 

[turtile]

Any chance that Zen4 is a 12 core die?
Sounds like a logical change to me, by that time 8 cores will be the minimum people buy, and if not you can still buy the DDR4 platform for low end.
6 cores on DDR5 doesn't sound right anyway now.
It would also llimit the changes needed to make an 96 cores Epyc.

Then CPU 6950X or 7950X will be 24 Cores...

or did AMD already say 8 cores per die for Zen4?

Given the die size required to make a 12 core, I don't think AMD will move to it until 3nm at the earliest. AMD wants to keep the die size around 65-80mm for optimum yield and I assume they will want to stay to the lower end as the costs become higher in the future for node shrinks. It's much more cost-effective to add more chiplets. I also think Zen 4 will have a brand new type of packaging to make the connection of chiplets easier.

They will also have to move mobile up to 12 cores unless they design two different architectures for consumer/professional.

 

[LightningZ71]

I feel that AMD is going to stay with 8 core CCDs for at least Zen 4 and 5. With each new generation having the expectation of significant IPC gains, it will require the cores to be wider and the caches to be larger. I think that AMD will be lucky to keep the CCDs at roughly the same size going forward, even assuming that the new process nodes scale as expected.

I would not be shocked if AMD, at some point, decided that they wanted to support a second core architecture that was smaller and more energy and area efficient in addition to their high performance Zen line. While I don't necessarily believe that big.LITTLE is the only path to optimizing a general purpose processor for single thread performance as well as energy efficiency, I do think that it will become a tool in AMD's belt at some point. Perhaps they will have desktop processors that include two performance CCDs, an IOD, and an efficiency CCD that is produced on an efficiency optimized node and rule set, with cores that are similarly designed. Assuming that such a thing is several years away, it's not unreasonable to also assume that they are using due stacking to put the IOD in the interposer, with the large L3, and not take a gigantic hit on the energy cost of having the CCDs talk to it because they are stacked.

 

[turtile]

I would not be shocked if AMD, at some point, decided that they wanted to support a second core architecture that was smaller and more energy and area efficient in addition to their high performance Zen line. While I don't necessarily believe that big.LITTLE is the only path to optimizing a general purpose processor for single thread performance as well as energy efficiency, I do think that it will become a tool in AMD's belt at some point. Perhaps they will have desktop processors that include two performance CCDs, an IOD, and an efficiency CCD that is produced on an efficiency optimized node and rule set, with cores that are similarly designed. Assuming that such a thing is several years away, it's not unreasonable to also assume that they are using due stacking to put the IOD in the interposer, with the large L3, and not take a gigantic hit on the energy cost of having the CCDs talk to it because they are stacked.

Papermaster said that that they won't use big little in a recent interview. According to a patent, it seems AMD is taking a more efficient approach. The patent shows a mico x86 execution area within the core. The complex will decide if the full core needs to turn on. If not, the micro x86 will execute and the normal core execution will be completely gated off to save energy.

I don't know if this makes sense in data centers so maybe this also hints at a possible split in consumer/professional lines.

 

[moinmoin]

I can imagine FPGA cores (alongside Zen cores) as the way forward. Like 512bit AVX could be done through combining two 256bit FPUs similar to how Zen 1 supported AVX2, whereas all the mess of AVX512 instructions could be executed on demand on FPGA cores. In general such an approach could turn out to be an exciting forward looking design depending on how flexibly parts of the Zen cores can interact with FPGA units.

 

[CakeMonster]

This is not my field of expertise, but would there be any reason for b.L except niche markets as we're shrinking fast anyway?

 

[HurleyBird]

This is not my field of expertise, but would there be any reason for b.L except niche markets as we're shrinking fast anyway?

Who knows about the the perf/W of this theoretical future alternative from AMD, but for embarrassingly parallel applications little cores can yield significantly better perf/area.

 

[moinmoin]

At this year's ISSCC AMD (in Sam Naffziger) once more talked about its chiplet evolution.

https://www.eetimes.com/amd-tsmc-imec-show-their-chiplet-playbooks-at-isscc/

Obviously only up to the status quo. Coy quote on what's to come:

Looking ahead, Naffziger sees a few possibilities like reduced connection overhead with interposers and denser interconnect, stacking memory directly on the compute die, and true 3D stacking beyond just memory die.

Anybody saw the presentation? Hope ISSCC males public a video of it later on.

 

[xilli_fiberbit]

Interesting leak on Genoa

https://twitter.com/x/status/1365981401808580614

:

96-cores (192 threads) : 8 cores per chiplet, 12 chiplets + an IO die
12-channel DDR5-5200
128 PCIe 5.0 lanes (160 for 2P)
320W TDP (cTDP 400W)
SP5 (LGA-6096) socket

A massive 6096 pins socket

 

[scineram]

Massive overkill for many customers. I bet Trento is a cheaper platform for normal buyers. 6 or 8 channel maybe?

 

[xilli_fiberbit]

Actual EPYC have 8-channel DDR4, Intel talked somewhere that it will push to 10-channel on Xeon... For Trento in Frontier it will be AI Optimized Zen3 ...

 

[Thibsie]

Actual EPYC have 8-channel DDR4, Intel talked somewhere that it will push to 10-channel on Xeon...

So going 12 channels seems adequate to me. Is it not ?

 

[xilli_fiberbit]

12-channel will be adequate, i would mean it's bigger number than Intel