Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Thibsie]

12-channel will be adequate, i would mean it's bigger number than Intel

I was rather thinking about number of channels Vs number of cores/chiplets added.
Sometimes now afaik Rome can be bandwidth starved so increasing the ram bandwidth seems obvious to me.

 

[jpiniero]

The higher TDP is I bet because they are still using GloFo 12(+?) for the IO die. That TDP is going to become a problem since you are going to need water.

 

[Thibsie]

The higher TDP is I bet because they are still using GloFo 12(+?) for the IO die. That TDP is going to become a problem since you are going to need water.

Well adding dies and keep using 7nm for the chiplets is already enough IMO, wether they still use Glofo IO die or not.
If they use 5nm which I doubt well, I'm puzzled.

 

[jpiniero]

Well adding dies and keep using 7nm for the chiplets is already enough IMO, wether they still use Glofo IO die or not.
If they use 5nm which I doubt well, I'm puzzled.

Not sure what you mean. The CPU chiplets are 5 nm. But surely there will still continue to be an IO die, even if they move to an active interposer.

 

[moinmoin]

Not sure I'd trust that leak. the number 96 for the amount of cores is nothing new and reminds me of the 48 cores originally rumored (and mentioned on leaked roadmaps) for Rome, which eventually got 64 cores. So I think 128 cores is still a posibility.

The higher TDP is I bet because they are still using GloFo 12(+?) for the IO die. That TDP is going to become a problem since you are going to need water.

I disagree, the node choice shouldn't make such a big difference for IO (unless they find one specifically optimized for IO which the ones talked about so far are not). For power consumption the uncore (which essentially matched the IOD) is pretty much the base level, and the biggest culprit for power consumption while idling is the IMC. Idle power has shown that consumption (given same RAM frequency, OCing RAM increases IMC power consumption further) rises linearly with the amount of channels, 2 for Ryzen, 4 for Threadripper and 8 for the current Epyc. So if 12 channels is true the IMC power consumption could be 50% over previous Epyc gens just due to the increasing amount of channels. The wildcard are the improvements in DDR5, I thought it would introduce more energy saving mechanisms as well as increase bandwidth so I personally wouldn't have expected an increase in amount of channels for Genoa. Will be interesting to watch how much these rumored specs match with the eventual product.

 

[eek2121]

The higher TDP is I bet because they are still using GloFo 12(+?) for the IO die. That TDP is going to become a problem since you are going to need water.

The higher TDP is actually due to the increase in core count as well as transistor density. It has little to do with the IO die. You won't need water since rack air cooling is very good.

 

[HurleyBird]

8 cores per chiplet, 12 chiplets + an IO die

Is that your speculation, or has that been leaked somewhere? Personally, I'm expecting 12-cour CCDs.

 

[uzzi38]

The higher TDP is I bet because they are still using GloFo 12(+?) for the IO die. That TDP is going to become a problem since you are going to need water.

Shrinking the I/O die wouldn't help much I don't think. More than anything else, it would be nice if AMD put some effort into power-gating their I/O dies.

Also, that TDP isn't so much a problem as it is the norm going forwards. TDPs are rising all around next gen - both DC CPU and GPU.

 

[uzzi38]

Not sure I'd trust that leak. the number 96 for the amount of cores is nothing new and reminds me of the 48 cores originally rumored (and mentioned on leaked roadmaps) for Rome, which eventually got 64 cores. So I think 128 cores is still a posibility.

That was because AMD increased the number of cores per CCD from 6 -> 8 for Zen 2. At this point it's a bit late for changes like that to take place

 

[jpiniero]

Is that your speculation, or has that been leaked somewhere? Personally, I'm expecting 12-cour CCDs.

The tweeter made a picture of a Genoa with 12 chiplets on it while taking about 96 cores. Plus it sort of works with 12 channels.

 

[turtile]

The higher TDP is I bet because they are still using GloFo 12(+?) for the IO die. That TDP is going to become a problem since you are going to need water.

It's more likely that the high TDP and 12 ch. memory are for more flexibility going forward. They can put out high clocked parts and have the ability to ship a future generation with 128 cores on the same socket without bandwidth limitations.

 

[dr1337]

That was because AMD increased the number of cores per CCD from 6 -> 8 for Zen 2.

This doesn't make any sense lol. zen 2 was always going to be two ccxs of four cores each... Its functionally similar to zen1 just with all of the IO moved off die. There was never a six core chiplet design, outside of speculation/fake leaks/rumors.

 

[Gideon]

I wonder if all of this means that we're also getting a cut down socket with 6 DDR5 channels and fewer PCIe 5.0 lanes.

Why I think it would make some sense is that it could also be reused for 90% of the Threadripper lineup, offering a nice mem-bandwidth boost to current 4-channel and not waste any pins. The maddest WX versions could still be LGA-6096 derived (they don't share much with the ordinary TR lineup anyway).

Also not all servers need the insane amount of memory bandwidth and PCIe lanes (particulairly as DDR5 will be expensive initially as well).

All in all even the cutdown version would still be a beast offering more I/O and memory bandwidth than current 8-channel EPYC parts.

 

[uzzi38]

This doesn't make any sense lol. zen 2 was always going to be two ccxs of four cores each... Its functionally similar to zen1 just with all of the IO moved off die. There was never a six core chiplet design, outside of speculation/fake leaks/rumors.

Are you sure about that - that Zen 2 was ALWAYS going to be 2x4c CCXes? Unfortunately, AMD have never commented on the mainstream Zen 2 design going up to 8 cores per CCD, but they have commented on Renoir getting bumped from 6 cores to 8 cores back when they launched it.

 

[moinmoin]

Are you sure about that - that Zen 2 was ALWAYS going to be 2x4c CCXes? Unfortunately, AMD have never commented on the mainstream Zen 2 design going up to 8 cores per CCD, but they have commented on Renoir getting bumped from 6 cores to 8 cores back when they launched it.

Renoir makes somewhat sense since that's a cut down design anyway (though that's likely a smokescreen as well considering the consoles were known to use 8c 2x CCX Zen 2 for some time already). But for the mainstream Zen 2 design you essentially suggest they had a 3 core CCX going before. That'd be such an asymmetric design that the whole package needs redesigning to switch from/to the comparably plain symmetric 4c CCX. And since the 4c CCX already existed I can't imagine any 3c CCX having got beyond the initial planning stage. In any direction that'd be such a waste of time.

 

[Gideon]

Renoir makes somewhat sense since that's a cut down design anyway (though that's likely a smokescreen as well considering the consoles were known to use 8c 2x CCX Zen 2 for some time already). But for the mainstream Zen 2 design you essentially suggest they had a 3 core CCX going before. That'd be such an asymmetric design that the whole package needs redesigning to switch from/to the comparably plain symmetric 4c CCX. And since the 4c CCX already existed I can't imagine any 3c CCX having got beyond the initial planning stage. In any direction that'd be such a waste of time.

Let's not forget that a 2-core CCX Zen+ Athlon desing does exist. They could have just done 4 + 2.

 

[moinmoin]

Let's not forget that a 2-core CCX Zen+ Athlon desing does exist. They could have just done 4 + 2.

That's even more asymmetric though. 🤯

 

[xilli_fiberbit]

This other leak said support in Genoa of AVX3-512 and bfloat16 instructions and others instructions not nammed. It saids above of 64 cores per socket but not said the exact number :

https://twitter.com/x/status/1366293479270150145

This can explain the 96 cores, because i think adding AVX3-512 and bfloat need more transistors

 

[moinmoin]

This can explain the 96 cores, because i think adding AV3-512 and bfloat need more transistors

Not necessarily. AMD could combine the two existing FPUs to enable 512 bit calculation, similarly to how Zen 1 achieved AVX2 256 bit calculation using two 128 bit FPUs. For a first implementation of AVX512 in Zen 4 I actually expect AMD to take this approach, native 512 bit would then be an improvement for Zen 5.

Edit: Btw. it's funny how the term "AVX3-512" was close to never used before this particular leak.

 

[DisEnchantment]

This other leak said support in Genoa of AVX3-512

No wonder there is no objection from AMD to LLVM and GCC organizing x86 feature set to fully include AVX512 in Feature level v4.
On the bright side, companies can at least deliver SW only for the later feature level which should help with the performance of most non manual tuned code for x86.
Difference is pretty stark in most cases between base x64 and native compilation for non tuned code.

 

[ThatBuzzkiller]

AMD should find a way to standardize hardware accelerated transactional memory once they're done implementing AVX-512 ...

Intel shouldn't be the only ones to keep dictating the x86 specifications so AMD should stop playing by Intel's terms and start making their own rules since their competitor's fabs are now failures ...

 

[soresu]

This can explain the 96 cores, because i think adding AVX3-512 and bfloat need more transistors

Mind you Zen2 doubled core counts despite going native 256 bit at the same time.

 

[Gideon]

Mind you Zen2 doubled core counts despite going native 256 bit at the same time.

True, but they also went from GF 12nm to TSMC 7nm, which is one of the best improvements in node tech in a while Samsung's EUV 5nm seems to be only about equal to that in power draw. If Apple's chips are any indication 5nm didn't really offer anywhere near as large power or SRAM (cache) shrinking benefits

 

[jpiniero]

I could see AMD doubling the L3 cache per chiplet too.

 

[uzzi38]

https://twitter.com/x/status/1366393857089409030

Die sizes as well now