Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

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Vattila

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Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

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What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts! :)
 
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nicalandia

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To be honest, I am not sure what the old "pressed" metal is, it is very thin. This is very thick, and could be made of a different alloy to help spread the heat better.
Also did you see how the Zen4 CCD are now Gold Plated? Or the diffusion layer has become gold colored?

This means that this pic is actually true.

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eek2121

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They didnt say anything about the Raphael IGP right? weird that it was this much secrecy around it.

Gamers Nexus confirmed it was a very basic GPU not meant for gaming. The leaks claim it has only 2CUs.
They definitely will not get 10% bump in frequency every generation. There's a reason why the ceiling has been in the 5 GHz range for long time now.

More likely you will see them do like Intel and a future generation that increases IPC will see a max clock below 5 GHz.

Zen 4 actually beats the 12900ks in terms of frequency. That is quite impressive for a node shrink. As transistors get closer together, hot spots become a huge issue. Looks like AMD found a way to overcome it and really crank things up.

It occurs to me we may possibly even see higher frequencies for the final chips, above what AMD demoed.

Also note that the 12900ks uses 300w when fully loaded, and it tops out at 5.0-5.2 ghz multicore.

AMD will likely avoid specifics until close to launch due to Raptor Lake. I suspect launch will be the last week of September.
 
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UsandThem

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eek2121

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2CU should be very close to a Vega 6, it is something at least. But i would like to know if it has any encoder/decoder.

Steve mentioned it, but not sure if he got confirmation from AMD about that part. I suspect it probably does, however.

Note that adding an onboard GPU means it can be also used for offloading certain compute tasks.
 

nicalandia

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More info on Zen4...


So 16C/32T at 5Ghz+ while Gaming...! Mighty Impressive

Quote "So in the game, we were running most of the threads around 5.5 (GHz), it depends on the game load, depends on the scene, of course, clock speed fluctuates up and down so somewhere between 5.2 and 5.5 is pretty common on all the threads playing that game. " Robert Hallock (AMD Director of Technical Marketing)

1653428396374.png


AT 170 Watt the MT Performance is boosted all around(Gaming and Render) due to those 16C/32T Staying at 5Ghz+
 
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Timorous

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3DCenter identified the demand and delivered:

Can't you jsut find a render that takes around 300s on a 12900K and see how long that takes on the 5950X. That would be the best comparison.

Having a list of Intel is faster at these places and AMD is faster at these places without noting how long the render took at each outlet is totally pointless because you can't just average out the deltas.
 

uzzi38

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2cu would probably be too low to provide encode/decode functionality. Considering most APUs have at least 6cu.
2WGPs sounds more reasonable, but that's not why. Encode/decode is handled by dedicated blocks anyway, the WGPs have nothing to do with.

Anyway, 2WGPs would be just like Intel in shipping an iGPU 1/3rd the size for desktop as they do for mobile.
 

Timmah!

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sounds like it's clocking higher than I thought... 5.2-5.5 on all thread is insane, speed demon design comes to my mind,,,,,


I dont think that he meant all-core turbo to be 5,2 to 5,5 during gaming. Just that iregardless of what core or core or cores are assigned to the game, all are capable to boost that high.

On topic of Adored TV - as he shows Lisa Su holding that prototype CPU in hand on Computex, he speculates those chiplets could actually hold more cores than 8 or that they might be space for another chiplet(s) - to support his former claim there will be more cores. Too bad at that particular time and place she says in the video literally "as you can see, Ryzen 7000 include up to 2 core chiplets, each with 8 Zen4 cores...." I presume this is why some people refuse to watch his stuff.
 

jpiniero

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On topic of Adored TV - as he shows Lisa Su holding that prototype CPU in hand on Computex, he speculates those chiplets could actually hold more cores than 8 or that they might be space for another chiplet(s) - to support his former claim there will be more cores. Too bad at that particular time and place she says in the video literally "as you can see, Ryzen 7000 include up to 2 core chiplets, each with 8 Zen4 cores...." I presume this is why some people refuse to watch his stuff.

Speaking of which, do we have any idea how big the Bergamo chiplet is?
 

Tuna-Fish

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So 16C/32T at 5Ghz+ while Gaming...! Mighty Impressive
Is this just a BS claim? The game doesn’t seem to scale much beyond 4 cores:

Reading comprehension!

Robert Hallock said:
So in the game, we were running most of the threads around 5.5 (GHz), it depends on the game load, depends on the scene, of course, clock speed fluctuates up and down so somewhere between 5.2 and 5.5 is pretty common on all the threads playing that game.

He's not saying 5.5 GHz all-core, he's saying that the chips can maintain 5.2-5.5 on all the cores that get stressed on this particular load. Based on deathBOB's link, that's probably something like 6 cores.
 

IntelUser2000

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Oct 14, 2003
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If what some are saying that Zen 4 didn't have significant core changes on leaks are true, then it makes sense why the gains are comparably small. You can't expect 15%+ per clock gains without substantial changes. Look what kind of changes were required in Zen 2/3, and Sunny/Golden Cove to get those kind of increases.

Also, as a side note, it was never impossible to increase number of decoders above 4. The increased transistors are non-linear due to variable instructions but they have done things to make up for that somewhat, so it's undesirable.

Gracemont also has 6 decoders. Yes it's using the 2x 3 wide clustered approach but Core uses Simple + Complex decoder config, so both are using ways to reduce transistor count.

Chips and Cheese showed that Gracemont is achieving 5-issue throughput consistently and even then it's limited by the backend, so it's not like it's weak at all.

Granted Golden Cove should have more at 1 Complex + 6 Simple.
 

Anhiel

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Is this just a BS claim? The game doesn’t seem to scale much beyond 4 cores:

View attachment 62056

from

Looks legit from what I saw with other CPU & game tests. Ofc the curve changes with different games but it's generally diminishing.

If what some are saying that Zen 4 didn't have significant core changes on leaks are true, then it makes sense why the gains are comparably small. You can't expect 15%+ per clock gains without substantial changes. Look what kind of changes were required in Zen 2/3, and Sunny/Golden Cove to get those kind of increases.

Also, as a side note, it was never impossible to increase number of decoders above 4. The increased transistors are non-linear due to variable instructions but they have done things to make up for that somewhat, so it's undesirable.

Gracemont also has 6 decoders. Yes it's using the 2x 3 wide clustered approach but Core uses Simple + Complex decoder config, so both are using ways to reduce transistor count.

Chips and Cheese showed that Gracemont is achieving 5-issue throughput consistently and even then it's limited by the backend, so it's not like it's weak at all.

Granted Golden Cove should have more at 1 Complex + 6 Simple.

Agree. They have to balance between energy saving margin and speed margins.
So based on these revelations and after back calculation I can say with certainty the demo ran without OC and very much at stock limit. The IPC at the low end seems to be 3%. There might be room for up to 20% power for OC, tweak and distribute... but I'm not too certain due to diminishing return.



So anyone has any idea of why two chipsets?

Because with only 8 cores each you get better yield with nearly no need failures on N5. And it's cheaper.
 

Saylick

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Sep 10, 2012
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On topic of Adored TV - as he shows Lisa Su holding that prototype CPU in hand on Computex, he speculates those chiplets could actually hold more cores than 8 or that they might be space for another chiplet(s) - to support his former claim there will be more cores. Too bad at that particular time and place she says in the video literally "as you can see, Ryzen 7000 include up to 2 core chiplets, each with 8 Zen4 cores...." I presume this is why some people refuse to watch his stuff.
Yeah, I think we're still stuck at 16C for Ryzen desktop this generation. When he mentioned his previous video and said that Zen 4 brings higher core counts, I think that was simply in reference to server Zen 4 parts, not desktop. Rome was 64 cores, Milan was 64 cores, and then finally with Genoa we get 96 cores. Bergamo brings 128 cores. Desktop Ryzen (not Threadripper)? 16 cores.

No clue here.

Had a bit of fun with that picture of "naked" CPU posted above in photoshop, so what do you say, is this possible? I just copied the core chipets and move the IO die and stuff around downward.
Haha, nice shop, but yeah, going to say that we're not getting mini-Sapphire Rapids on that socket, at least not without a new CCD entirely because the current approach still uses traces under the substrate. I imagine an approach similar to what you've shown will require embedded bridges, likely some of which allow for CCDs to daisy chain off of other CCDs.

So anyone has any idea of why two chipsets?
As others have said, it's because it eliminates other, costlier components. Plus, it simplifies the chipset supply if you only need to produce one chipset die and just use more of them for higher end mobos. Think of it as AMD producing a chipset die that caters to the vast majority of the mobo market, which is the B650 mobo. One of the chipset dies is enough for B650 while a cutdown version of that die, as yields permit, will be used for budget A-series mobos, and two of them will be used for the high end X670 and X670E mobos. One die serves the entire market, not unlike how AMD used to design mid-range GPUs and then doubled them up in Crossfire to address the high end market.
 
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