They could stand to have something in between the full Epyc SP5 (768-bit memory interface, etc) and Ryzen AM5 (128-bit memory, etc). With Genoa, Epyc is now 6x the desktop part rather than just 4x. This isn’t just for HEDT; there are also workstation and lower end server parts that don’t need a full size SP5 socket.A TR is 4x the number of chiplets as Ryzen, active or not. The whole platform is just expensive to produce.
I have thought that the best way to go would be what Apple did with the M1 Ultra. Make a large APU (16-core) and put two of them together for 2x everything. Either that or just make a desktop sized IO die that can connect to a second IO die for 256-bit memory and up to 4 cpu chiplets. That would allow for very cheap HEDT, workstation, and low end server implementations without using an expensive Genoa IO die and package. Genoa tends more towards HPC than generic server.