Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

Vattila

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Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

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What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts! :)
 
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scannall

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I'm thinking they'll likely go wider. 6 ALU's, 3AGU's/Load-Store units. 3 FPU's per core. Clockspeed for increased performance is dead, and has been for a while. If you can't go faster, go wider. SMT4? No way. Too many transistors for diminishing returns, particularly in x86 land. SMT2? (3 threads per core) Pretty unlikely, but possible. Pushing transactional memory is going to happen at some point. Unlike Intel's foray into that though, it has to be across the entire stack. Not used as an artificial product segmentation gimmick. Another thing that will be coming, but not yet would be unified memory/storage. Too much work to do in OS's and software still. The speed is getting pretty close, but not quite there yet. Maybe by PCIe 6, or whatever follows PCIe.

I also expect more security hardening. They have a solid lead here, and will likely keep pushing on that.
 

soresu

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Another thing that will be coming, but not yet would be unified memory/storage
Dubious, requires a clear successor to Flash with DRAM like speed to be truly effective - like the purported traits of Nantero NRAM, that has 256 gbit dies on their roadmap at SLC bit density (MLC supposedly possible too).
 
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scannall

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Dubious, requires a clear successor to Flash with DRAM like speed to be truly effective - like the purported traits of Nantero NRAM, that has 256 gbit dies on their roadmap at SLC bit density (MLC supposedly possible too).
It's a ways out. Both speed issues to work out, and probably tougher are OS and software issues. As a wild guess, not before 2027 to 2030. But at some point it will happen.
 

.vodka

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New socket for Zen4 Epyc/TR/Ryzen is a given, and also confirmed by the Milan presentation (Genoa will use SP5)

https://www.anandtech.com/show/13490/cadence-and-micron-ddr5-update

cadence_ddr5%20adoption.jpg


Introducing DDR5 in 2021 with new sockets for the entire lineup is the next step. Also, PCIe5 is likely to be in there, too. The spec was finished in May 2019, and it seems to take ~2 years from that point to hardware on shelves (PCIe4 Oct2017/ AM4 Zen2 in 2019), also lining up for 2021.

New socket also means not having to deal with preexisting contraints like Zen2's chiplet paradigm had to do with to maintain AM4/SP3 compatibility. So I'd think there could be some further advances in this area with interposers or more creative chiplet uses.

I also agree Zen4 will go wider to improve performance while also continuing Zen/Zen+/Zen2's path towards getting ever closer to the practical ~5GHz limit on more cores. Zen2's boost algorithm will evolve to be even more effective at getting 100% out of each individual piece of silicon out of the fab.

I expect AVX-512 support in Zen4, just like Zen/Zen+ supported AVX/2: be compatible, but execute at half rate. As far as I understand AVX512 is nice to have from an instructions point of view, apart from the throughput increase if one were to do a full rate implementation of it. If it happens, I wonder which circles of AVX-512 compatibility hell will they support.

----------------------------------------------------------------------

Also, AMD liked the game around the number 7 for Zen2's launch (even going to a launch on a Sunday, and launching products on the 7th of each month), so this is another ideal meme worthy launch for them. Blatantly stolen from the internet hivemind:
  • AM5 + Zen4 (just rename it to Zen5, lol)
  • DDR5
  • PCIe 5.0
  • Using some form of TSMC's 5nm node?
  • Launching 5/5/2021 (2021 = 2+2+1 = 5)

------------------------------------------------------------------

edit: Just had a thought.

I remember reading that AM4 was somewhat constrained in what capabilites it exposed out of the Zeppelin SOC while maintaining compatiblity with faildozer parts. Motherboard vendors were pessimistic about it from the start considering the previous five years of AMD's history.

For example, Zeppelin had 32 PCIe lanes in it, only 24 were used for AM4.

This time it's a clean slate for greatness considering what Zen has sparked in the industry, not to mention the sales. Everyone will be willing to do interesting things with it, or go the extra mile on connectivity.

If AM5 does some creative chiplet usage or moves to an interposer, I'd love to see an APU with an HBM2/3 stack in there. That would be awesome, either as another cache level for general usage or to give the iGPU some juicy bandwidth to work with.
 
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NTMBK

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It would be very nice if AM5 made more use of the SoC's capabilities, instead of e.g. leaving the NIC disabled. Cheaper boards, smaller boards, lower power.
 
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soresu

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Atari2600

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Within reason, I would be surprised if AMD broke cooler compatibility again with AM5 as they did with AM4 - they have a good record of keeping platform compatibility in general.

Ach, a $5-10 bracket will fix that.

I for one would hope they don't compromise a 5 year lifespan platform for the sake of a few quid bracket!
 
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soresu

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Ach, a $5-10 bracket will fix that.

I for one would hope they don't compromise a 5 year lifespan platform for the sake of a few quid bracket!
I'd argue the opposite - getting an AM4 cooler with everything in the box was a pain in the ass for quite a while after initial Zen release in 2017.

There were less than half a dozen pre-packed choices at launch, the rest were brackets as you say, but separate things none the less - I'd rather have everything in the box to be honest, it's not like AMD didn't manage to retain socket cooler compatibility from AM2 to AM3+ at least, which was a much longer timeframe than 2017-2021.

The problem wouldn't exist at all if more cooler manufacturers just put the damn brackets in the box as soon as they were available as a 2.0 version of the product or something.
 

scannall

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I'd argue the opposite - getting an AM4 cooler with everything in the box was a pain in the ass for quite a while after initial Zen release in 2017.

There were less than half a dozen pre-packed choices at launch, the rest were brackets as you say, but separate things none the less - I'd rather have everything in the box to be honest, it's not like AMD didn't manage to retain socket cooler compatibility from AM2 to AM3+ at least, which was a much longer timeframe than 2017-2021.

The problem wouldn't exist at all if more cooler manufacturers just put the damn brackets in the box as soon as they were available as a 2.0 version of the product or something.
Originally, motherboard manufacturers and other suppliers didn't really invest much in the platform. Kinda makes sense given AMD's appeal during the construction core era. Should they change the socket enough to require a new bracket/cooler then I'm sure there would be plenty of options this time around.
 

ClockHound

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I'm going with All Of The Above plus more.

Fully expect an extra couple hot hot 5.5Ghz cores in a user-selectable extra chiplet - made at Intel, so they can keep those 14+++++++nm shareholder profits burning. And give the INTELigentsia a hot shiny sliver of a bragging point in their dark days to come. :p
 

H T C

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I'm going with the "lower clocks but 15%+ increased IPC VS ZEN 3" camp.

As the process gets smaller and smaller, the heat gets more and more concentrated to the point high speeds aren't possible anymore, despite the chiplet approach.

How to get around the lower clock speeds and still make it an upgrade? Increase the IPC enough to offset the lower clocks: i'm guessing ZEN 4 will max out @ 4GHz if that but, in return, the IPC improvement will more than make up for it.

Time will tell ...
 
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Thunder 57

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Couldn't we wait on speculation until Zen 3 was out :p ? I voted for all except SMT4 and HBM. Not so sure on HBM, could be a thing for APU's if it cost effective. I'm guessing AM5 is LGA as well. There will probably be AVX 512 support, but how much and whether they do 2 x 256 or 512 I won't speculate on just yet.

I wouldn't be surprised if we saw more high end APU's as well. Think eight core with some kind of RDNA GPU.
 

soresu

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Couldn't we wait on speculation until Zen 3 was out :p ? I voted for all except SMT4 and HBM. Not so sure on HBM, could be a thing for APU's if it cost effective. I'm guessing AM5 is LGA as well. There will probably be AVX 512 support, but how much and whether they do 2 x 256 or 512 I won't speculate on just yet.

I wouldn't be surprised if we saw more high end APU's as well. Think eight core with some kind of RDNA GPU.
Still awaiting a Vega M equivalent from AMD - the same APU segment I mean, that was a huge processor package size, surely AMD can do a better job.
 

HurleyBird

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I ended up voting for everything. Now, I really doubt Zen 4 will have everything listed, but taken individually I see each feature as >50%.

The possible exception being AVX512, depending on whether you mean 2x256 or 1x512. I see the former as >75% and the later as <25%.
 

beginner99

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I think for Ryzen the socket will stay the same and will remain on ddr4. For epyc socket will probably change and move to ddr-5. That's the beauty of the IO die.
 
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soresu

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I think for Ryzen the socket will stay the same and will remain on ddr4. For epyc socket will probably change and move to ddr-5. That's the beauty of the IO die.
Could be, could be that TR4 will go DDR5 leaving the mainstream on DDR4 until prices come down from crazy town.
 

Richie Rich

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Super hard to predict Zen4 when we know almost nothing about Zen3.
Zen4 will be evolution of Zen3:
  1. - DDR5, new socket AM5/SP5,
  2. - PCIe5.0
  3. - 64 MB of L3 cache (Zen3 probably 48 MB)
  4. - maybe 10-12 core CCD (96MB L3 cache)
  5. - uarch lower jump than Zen2, keeping 6xALUs+4xFPU(8pipes)+SMT4, optimizing new Zen3 uarch, sizes of buffers (ROB, schedulers), something like A11 -> A12, however solid +15% IPC boost
  6. - AVX512 half speed (256 bit)... assuming Zen3 will have Zen2 FPUs, just doubled pipes to support SMT4.
  7. - AVX512 full speed (512 bit) for Zen 5
 
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A///

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1. New Socket - AM5

2. DDR5 Support - This time around major memory makers are on the ball.

3. PCI-E 5.0

4. 2+ cores across the board

5. New chiplet design

6. IHBM

5. AVX 512 support

6. Integrated co-processors? Link to a small FPGA on X770 boards?


There is no SMT4. This has been thrown around for a while. There is no point in it. Performance isn't linear the more threads you have.
 

amrnuke

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There is no SMT4. This has been thrown around for a while. There is no point in it. Performance isn't linear the more threads you have.

There is little point in it for Ryzen, but there may be a point in it for Epyc. Just depends on the implementation and how much value the design team is likely to get out of completely redesigning the front end to handle scheduling for 4 threads on 1 core - for a core design that will be used across mainstream, HEDT, and server - when it will have little benefit (may actually be detrimental) for their goals on Ryzen.
 

A///

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There is little point in it for Ryzen, but there may be a point in it for Epyc. Just depends on the implementation and how much value the design team is likely to get out of completely redesigning the front end to handle scheduling for 4 threads on 1 core - for a core design that will be used across mainstream, HEDT, and server - when it will have little benefit (may actually be detrimental) for their goals on Ryzen.
The only "comparison" if you could call it that to any other processor is IBM's niche Power, but they're unoptimized and not made for general use so next to your typical x86-64 processor they're hot garbage, but again different uses. On the consumer side I have a tough time imagining just how much an uphill battle it would be to get software companies to optimize for 4 threads over the current two, which some still have trouble with or shall I say "trouble." In the right setup, Power does tasks well at lower power and heat.

But, as I said, I have a tough time imagining the need of 4T on a consumer processor. Maybe in a decade? I don't even know how this rumor got started apart from the Scottish youtuber, because it was floating around long before he mentioned it.

IDK what AMD have in plan. I hear enough rumors and spoke to enough industry leakers but eh, it's all a wash for me until I see it in physical format or it's formally announced. And, by it, I mean any company whose employees reach out. I'd feel more sorry for Intel if Epyc in 2-3 years manages to double down on their current lead, or more. We have a long ways to go before AMD's marketshare as a whole becomes a significant number. I can't remember AMD being complacent and milking customers back in the warm and glorious days they led the market and Intel had to bribe their way into every OEM's cold, dead heart.
 

maddie

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There is little point in it for Ryzen, but there may be a point in it for Epyc. Just depends on the implementation and how much value the design team is likely to get out of completely redesigning the front end to handle scheduling for 4 threads on 1 core - for a core design that will be used across mainstream, HEDT, and server - when it will have little benefit (may actually be detrimental) for their goals on Ryzen.
This is something rarely discussed, at least to my knowledge. IF, more businesses are migrating their everyday work to the cloud, AND with the increasing single thread performance of the latest CPUs, then why would any cloud provider want to assign high performance threads to low demand work?

In this case, would it not make more business sense to share these types of workload with more threads on the same core? What am I missing?
 

Tup3x

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Personally I doubt that the Zen 4 comes with PCI-E 5 but Zen 5 likely could. It definitely has DDR5 and AVX-512 support. Maybe more cores too (or at least 12 core version being more mainstream). If the new CCX allows more core combinations then we might see some new core count versions (like 10). That might already happen with Zen 3 though.
 
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