Solved! Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[uzzi38]

Gracemont performs better than Zen 2 and worse than Zen 3. Throw 16 of them in a chip along with the Raptor Cove, and assuming Intel isn't power limited, the chip will be 40-50% faster than a 5950X. That means a 6950X will need to be 40%-50% faster to tie with the Intel chip. That is why AMD needs a 24 core SKU. Note that Raptor Lake is currently rumored to launch BEFORE Zen 4. If Raptor Cove is power limited, then AMD doesn't need to make up such a wide gap.



125W PL1, 241W PL2. That is from the Gigabyte leak. Raptor lake apparently has a lower PL2 (I would have to dig up the Igor's lab article).

Nah what AMD needs is higher power limits to keep up in all MT workloads, that's all. Which is exactly why the 170W TDP (230W PPT) SKU exists.

24 cores is unnecessary. Zen 4 cores themselves are significantly stronger, plus you get an extra 25-30% perf from higher power limits.

 

[DrMrLordX]

Internal engineering samples can be different than the samples sent to partners for validation, right? When I said sampling, I meant the ones sent out to partners for validation.

I mean maybe? But usually once they have an ES in the intended final configuration, it's not more than a few months to QS.

 

[A///]

I was under the impression that it was max sustainable power consumption of AM5 socket, like 140W is for AM4.

As said earlier, AM4 can sustain higher power consumption levels. It simply doesn't mean that AMD or Intel in any case would release a part with that much power use. Ideally you want a design that puts out more performance while using similar power or even a bit less. Thank goodness that neither AMD nor Intel have a Tim The Toolman Taylor approach to design!


Apologies for the very late reply. I was out of the country.

 

[eek2121]

A thought I had. Ryzen will be 5 years old next year, right? 5 years old, 5nm, DDR5, (AM5)...

Sensing a pattern here...

 

[Abwx]

A thought I had. Ryzen will be 5 years old next year, right? 5 years old, 5nm, DDR5, (AM5)...

Sensing a pattern here...

5GHz (officially) and Zen 5 on the work.

 

[uzzi38]

A thought I had. Ryzen will be 5 years old next year, right? 5 years old, 5nm, DDR5, (AM5)...

Sensing a pattern here...

If we count Genoa then we get PCIe 5 too.

5GHz is the tricky bit though... To be frank I genuinely wouldn't be surprised if max clocks stay where they are or even drop ever so slightly (though not below Zen 2 clocks).

 

[DisEnchantment]

5GHz is the tricky bit though... To be frank I genuinely wouldn't be surprised if max clocks stay where they are or even drop ever so slightly (though not below Zen 2 clocks).

For the desktop Zen4, 5GHz most likely is not going to be an issue if the AVX512 is not engaged.
20% speed improvement at same power or 43% power reduction (N7 --> N5P).
Zen3/5950X boost is already hovering close to 5GHz (and it can be sustained on single core, on my 5950X I see sustained 5GHz on single core) and 43%power reduction (assuming same CPU TDP) would allow this to be maintained consistently even with the increased core complexity.
But I would prefer the power reduction over the speed boost if the core is throughly improved. Even a 35% power reduction will give so much headroom for sustaining boost.

 

[Mopetar]

5GHz (officially) and Zen 5 on the work.

With that many 5's lining up, I'd just skip Zen 4 (or use it for something else like half generation parts like Zen 3D or just some of the APUs) and skip right to Zen 5.

Frankly we'd be there if Zen+ had just been called Zen 2.

 

[Abwx]

With that many 5's lining up, I'd just skip Zen 4 (or use it for something else like half generation parts like Zen 3D or just some of the APUs) and skip right to Zen 5.

Frankly we'd be there if Zen+ had just been called Zen 2.

Zen + is the same chip than Zen, the difference is in the microcode and a slightly improved process, so that was a firmware update more than anything else and couldnt be honestly called Zen 2, that s the same evolution as Intel s SKL/KBL to CML.

I forgot to add that they re on the road for 5 billions quarterly revenue, possibly that they ll break this level with Zen 4 since current server marketshare is at 16% or so.

 

[DisEnchantment]

• AMD coming out and confirming PCIe Gen5 support for AM5 and debunking rumors.
• Also they don't foresee big.LITTLE architecture at the moment for Zen
• CVML blocks within Ryzen (Zen4 probably)
  • This is very interesting, basically what I have blabbering for a bit about what is present in Snapdragon that allows all those features he was talking about related to camera to be done in the DSP block at low power and continuously without powering up the cores
  • I wonder if they would go with soft logic block or hard DSP blocks from Cadence
• For Ryzen Mobile, expect more power gateable blocks to increase efficiency
• Power Management framework

Hallock is purposefully vague, seems they are waiting for Lisa to deliver the punch lines

 

[HurleyBird]

AMD coming out and confirming PCIe Gen5 support for AM5 and debunking rumors.

The only rumors are that Zen 4 won't support PCIe 5. There are exactly zero rumors that AM5 as a platform won't ever get PCIe 5 support.

So, reading between the lines Zen 4 is intended to support PCIe 5, but Hallock is leaving wiggle room in case it doesn't play out for whatever reason.

Otherwise, Hallock is screwing up the messaging and generating confusion. As someone who isn't a big fan of Hallock, this is a scenario that I would only find moderately surprising.

 

[andermans]

The only rumors are that Zen 4 won't support PCIe 5. There are exactly zero rumors that AM5 as a platform won't ever get PCIe 5 support.

So, reading between the lines Zen 4 is intended to support PCIe 5, but Hallock is leaving wiggle room in case it doesn't play out for whatever reason.

Otherwise, Hallock is screwing up the messaging and generating confusion. As someone who isn't a big fan of Hallock, this is a scenario that I would only find moderately surprising.

I think I'd read the statements as AM5 gets PCIE5 in 2022, which doesn't have to be Zen4 but hard to see it being anything else. Wonder how bendable that wording ends up being though.

 

[leoneazzurro]

I think I'd read the statements as AM5 gets PCIE5 in 2022, which doesn't have to be Zen4 but hard to see it being anything else. Wonder how bendable that wording ends up being though.

In fact, he says explicitely "In 2022 Ryzen will have a new platform having for key ingredients DDR5 and PCI-E 5 (and compatibility with old coolers)" and just a few seconds later he denies the rumors of it having gen4. Now, speaking only about the socket will be really odd, especially because he's talking about the whole platform, and if the socket supports PCIE5 but the CPU doesn't, there is no way "to get PCIe5 in 2022. The two AM5 products are Rembrandt (being this an APU designed for mobile first it's very unlikely it will have PCI-E) and Raphael.

 

[Joe NYC]

In fact, he says explicitely "In 2022 Ryzen will have a new platform having for key ingredients DDR5 and PCI-E 5 (and compatibility with old coolers)" and just a few seconds later he denies the rumors of it having gen4. Now, speaking only about the socket will be really odd, especially because he's talking about the whole platform, and if the socket supports PCIE5 but the CPU doesn't, there is no way "to get PCIe5 in 2022. The two AM5 products are Rembrandt (being this an APU designed for mobile first it's very unlikely it will have PCI-E) and Raphael.

IMO, Rembrandt, likely being a monolithic design and targeting low power applications will not have PCIe5.

Raphael, which will have a separate IO die, which will be a derivative of full Genoa IO die, will likely have PCIe5.

 

[leoneazzurro]

Yes, it's what I said. Raphael will have also a iGPU, it seems.

 

[soresu]

Raphael, which will have a separate IO die, which will be a derivative of full Genoa IO die, will likely have PCIe5.

I could have sworn someone already said that AM5 will start out minus PCIe5, which IMHO considering the whole ruckus over the extra thermals that the PCIe4 transition cost the chipset on AM4 it's not a great surprise that they would want to wait until they can manage it with passive cooling.

 

[Thibsie]

I could have sworn someone already said that AM5 will start out minus PCIe5, which IMHO considering the whole ruckus over the extra thermals that the PCIe4 transition cost the chipset on AM4 it's not a great surprise that they would want to wait until they can manage it with passive cooling.

That's what I remember to

 

[leoneazzurro]

I could have sworn someone already said that AM5 will start out minus PCIe5, which IMHO considering the whole ruckus over the extra thermals that the PCIe4 transition cost the chipset on AM4 it's not a great surprise that they would want to wait until they can manage it with passive cooling.

I think that the confusion comes from a lot of apparently contradicting rumors, but the general idea I made from all of these is quite simple::

- First AMD product supporting DDR5 will be Rembrandt, an APU that will start only mobile - this wil come probably at CES. This APU will not support PCI-E 5 (power consumption in mobile). This APU seems to support DDR5 and LPDDR5 only.
- It is quite possible that, as happened with Cezanne, around middle of the year this APU will come in desktop form, almost exclusively for OEMs
- Obviously if it will come in desktop, it will need AM5 platform because it supports DDR5 only, but, as this APU will not support PCI-E 5, initial AM5 machines will be stuck to PCI-E 4
- PCI-E 5 will arrive with Zen4 at the end of the year.
- There will be some sort of segmentation of mainboards, with top-end getting PCI-E 5 and lower end getting PCI-E 4 or PCI-E 5 only for the VGA, this happened as well with Zen2. Reasons are costs and power consumption.

This ofc is only speculation, but it is quite logical and it matches the rumors so far as well as the AMD platform hystory.

 

[Abwx]

- Obviously if it will come in desktop, it will need AM5 platform because it supports DDR5 only, but, as this APU will not support PCI-E 5, initial AM5 machines will be stuck to PCI-E 4

On DT there s a chipset to accomodate PCIE5 if ever RMB has a fast enough link that would be disabled for mobile.

 

[leoneazzurro]

On DT there s a chipset to accomodate PCIE5 if ever RMB has a fast enough link that would be disabled for mobile.

I mean, we already saw how it worked out for Renoir and Cezanne, desktop version. It's very unlikely to get PCI-E5 with Rembrandt at all.

 

[Mopetar]

Zen + is the same chip than Zen, the difference is in the microcode and a slightly improved process, so that was a firmware update more than anything else and couldnt be honestly called Zen 2, that s the same evolution as Intel s SKL/KBL to CML.

Zen 2 is just the marketing name so they could do anything they wanted to with it. The APUs used to be on a different numbering system until they unified everything in the 5000-series with Zen 3. I will give AMD some respect for not calling it Zen 2, but I suspect that they didn't want to make the Zen line seem lackluster by using Zen 2 for Zen+

That kind of shenanigans is a lot more common in the GPU market though. A lot of new cards end up being rebranded old generation parts. Polaris was pretty much the 400 and 500 series and I think the changes they made there were even less than what we saw with Zen+

 

[DisEnchantment]

https://twitter.com/i/web/status/1449331716976435203

Isn't this the 128 Core CPU.
Seems ExecuFix is saying it is Zen4 based.

But from leaked manual you can see



CCD: 0 to 11 (12 CCDs)

From Family 19H PPR

Instances of core registers are designated as ccd[n:0]_lthree[n:0]_core[n:0]_thread[1:0]. Core registers may be shared at
various levels of hierarchy as one register instance per node, per L3 complex, per core or per thread. The absence of the
instance parameter _thread[1:0] signifies that there is not a specific instance of said register per thread and thus the
register is shared between thread[1] and thread[0]. Similarly, the absence of the instance parameter _core[n:0] signifies
that there is not a specific instance of said register per core and thus the register is shared by all cores in that L3 complex,
and so on. The absence of instance parameters indicate there is one shared register at the node level. Software must
coordinate writing to shared registers with other threads in the same sharing hierarchy level.

Either this is a 96 Core, or it is a new model which was not part of the leak.

 

[andermans]

https://twitter.com/i/web/status/1449331716976435203

Isn't this the 128 Core CPU.
Seems ExecuFix is saying it is Zen4 based.

But from leaked manual you can see

View attachment 51513

CCD: 0 to 11 (12 CCDs)

From Family 19H PPR


View attachment 51515

Either this is a 96 Core, or it is a new model which was not part of the leak.

Could they not have more cores/CCD for this?

 

[DisEnchantment]

Could they not have more cores/CCD for this?

As per the leaked manual, lthree[n:0]_core[n:0] --> In Zen4 it is lthree0_core[7:0]
So it is 0 to 7, core for each L3/CCD. So 8 eight cores/CCD.

Could be a different Model. When I checked the PPR for the other models within the Zen3 family, there are very specific CCD related info for register instances.
So seems, the leaked data was for Genoa, This one is not known at the moment.

Lets see, I think Intel showing off their roadmap this month is going to make AMD share more info, however vague it may be.

 

[yuri69]

Both Bergamo and Genoa belong to AMD Family 19h but the models are completely different - Bergamo being much "newer".

* 00A10F00 aka Models 10h-1Fh - Rolling Stones - Genoa
* 00AA0F00 aka Models 100h-10Fh - ??? - Bergamo