Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

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Vattila

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Oct 22, 2004
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Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

Untitled2.png


What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts! :)
 
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jamescox

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Nov 11, 2009
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Charlie at SemiAccurate apparently confirming 128-core "Bergamo":

"More than just a 128c monster — AMD has an upcoming 128 core CPU called Bergamo and what it signifies is more important than that it is. SemiAccurate thinks Bergamo is the first of a new class of CPUs with more to follow."

What is AMD's Bergamo CPU? - SemiAccurate
I can’t read the article. Makes me wonder if it is a stacked device with at least 2 layers of cpu die. The 96 core thing is still a bit odd, but didn’t they talk about a 48 core with Rome before revealing that it could go up to 64? Some 48 core versions of Rome / Milan are asymmetric since they use 6 CCD rather than 8 ccd with cores disabled. The 96 core might be 16 die x 6 core using multi-layer stacks rather than an asymmetric configuration. It would be interesting if there is some sales data on how well the 48 core Rome / Milan is selling.
 

Doug S

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Feb 8, 2020
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Some interesting tests by TSMC about in-chip water cooling.



I'm sure this is something the big cloud providers would love to see. They'll just have to figure out how to go from delivering 10-20 kW per rack to delivering 100-200 kW per rack (if they go from ~260 watts to 2.6 kw per socket)
 

Vattila

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Oct 22, 2004
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Some interesting tests by TSMC about in-chip water cooling.

Interesting indeed. Underfox's recent patent tweet included a couple of AMD patents on cooling and thermal management, so there is intense R&D in this field, it seems. I guess we will see more ingenious in-package thermal management and cooling solutions in the near/medium future, improving on the brute force heat sink cooling used today.
 

Kepler_L2

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Sep 6, 2020
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Interesting indeed. Underfox's recent patent tweet included a couple of AMD patents on cooling and thermal management, so there is intense R&D in this field, it seems. I guess we will see more ingenious in-package thermal management and cooling solutions in the near/medium future, improving on the brute force heat sink cooling used today.
Not surprising, it's pretty much a requirement for logic-on-logic 3D stacking.
 

Ajay

Lifer
Jan 8, 2001
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Some interesting tests by TSMC about in-chip water cooling.


While worth a shot, I think using copper** conductors would be a better choice. While it may be more complex to achieve mechanically (bonding, dealing with differing coefficients of expansion, etc.), that approach would more effective at getting heat out of 3 dimensional silicon structures. The issue with current discussions about using 'vias' to conduct head out of silicon dice is that the conversation revolves around the current stepped inverted cone used. The very small final discs in metal layers just above the transistor layer cannot conduct much heat. I think that constant radii cylinders (or rectangular prisms) will need to be used, though the area under such structures will be no-go for xtors. Getting those 'fins' spread out and bonded to redesigned heat spreaders are all very challenging problems. Just my 2 cents.

** probably some alloy rather than pure copper.
 
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maddie

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Jul 18, 2010
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While worth a shot, I think using copper** conductors would be a better choice. While it may be more complex to achieve mechanically (bonding, dealing with differing coefficients of expansion, etc.), that approach would more effective at getting heat out of 3 dimensional silicon structures. The issue with current discussions about using 'vias' to conduct head out of silicon dice is that the conversation revolves around the current stepped inverted cone used. The very small final discs in metal layers just above the transistor layer cannot conduct much heat. I think that constant radii cylinders (or rectangular prisms) will need to be used, though the area under such structures will be no-go for xtors. Getting those 'fins' spread out and bonded to redesigned heat spreaders are all very challenging problems. Just my 2 cents.

** probably some alloy rather than pure copper.
Won't you get capacitance effects in that copper layer so close to the electron flows? If it isn't close then it's the same as the heatsink.
 

jamescox

Senior member
Nov 11, 2009
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Won't you get capacitance effects in that copper layer so close to the electron flows? If it isn't close then it's the same as the heatsink.
They already have to take parasitic capacitance into account. Modern chips are a bottom layer of transistors and then many metal interconnect layers on top. All of the interconnect traces have to be assigned some parasitic capacitance and resistance in circuit simulations. It is also coupled with the charge state of traces above and below each trace for around 10 to 12 layers of interconnect. This blows up into a big compute problem quickly.

I don’t know about the manufacturing process for this though. TSVs are made by etching deep into the wafer and then exposed by polishing down the wafer from the other side. This doesn’t seem workable for placing directly below devices since the devices must have a layer of silicon below.

I guess we are going to see some possibly exotic solutions, but probably not for a while. Although, I may have said that in the past about AMD and was wrong. I think they might be able to do at least 2 layers by just using well binned devices at lower clocks. If they can keep it down to 4 or maybe 6 die stacks, then they could use LSI or other stacking tech for connecting CCD stacks to the IO die. I was expecting the initial version of Genoa to use serial connections, but it is not very power efficient with another doubling of speed. Using LSI would make sense, but it does require that the chips are adjacent, so it limits the number of CCD. The 6 stack solution is still asymmetric with respect to the 4 IO die quadrants, but they already make such devices. Perhaps the 128-core device comes a bit later and uses 4 high stacks with some exotic cooling.
 

soresu

Diamond Member
Dec 19, 2014
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While worth a shot, I think using copper** conductors would be a better choice. While it may be more complex to achieve mechanically (bonding, dealing with differing coefficients of expansion, etc.), that approach would more effective at getting heat out of 3 dimensional silicon structures. The issue with current discussions about using 'vias' to conduct head out of silicon dice is that the conversation revolves around the current stepped inverted cone used. The very small final discs in metal layers just above the transistor layer cannot conduct much heat. I think that constant radii cylinders (or rectangular prisms) will need to be used, though the area under such structures will be no-go for xtors. Getting those 'fins' spread out and bonded to redesigned heat spreaders are all very challenging problems. Just my 2 cents.

** probably some alloy rather than pure copper.
The basic research behind this technology is already done and dusted - theory tested and proven.

Check out DARPA's ICEcool project from the last decade:



This news from TSMC is basically them figuring out how to take that research and implement it in a mass manufactured process node, which is much more viable due to the 3D tooling they have expanded into for newer generations with AMD et al.
 

Ajay

Lifer
Jan 8, 2001
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The basic research behind this technology is already done and dusted - theory tested and proven.

Check out DARPA's ICEcool project from the last decade:



This news from TSMC is basically them figuring out how to take that research and implement it in a mass manufactured process node, which is much more viable due to the 3D tooling they have expanded into for newer generations with AMD et al.
That's refrigerant based cooling.
 

jpiniero

Lifer
Oct 1, 2010
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I can’t read the article. Makes me wonder if it is a stacked device with at least 2 layers of cpu die. The 96 core thing is still a bit odd

I'd say that Genoa looks like Rome, except it has 12 dies instead of 8. 96 was probably chosen because of power consumption and perhaps space. Have to read that article to see what Charlie thinks but Bergamo could be stacked dies or stacked on top of the IO die. Either way the power consumption is going to be crazy.
 

Timorous

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Oct 27, 2008
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I'd say that Genoa looks like Rome, except it has 12 dies instead of 8. 96 was probably chosen because of power consumption and perhaps space. Have to read that article to see what Charlie thinks but Bergamo could be stacked dies or stacked on top of the IO die. Either way the power consumption is going to be crazy.

Stacked on the IO die would mean the IO Die and chiplets are on the same node right? TSMC don't do cross node stacking or is it that they don't do cross node stacking yet?
 

Abwx

Lifer
Apr 2, 2011
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Ajay

Lifer
Jan 8, 2001
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Some news on Zen 4 for DT.





Patrick Schur
@patrickschur_

The exact TDP numbers for Raphael are 65, 95, 105, 120 and 170 W.
12:19 nachm. · 14. Juli 2021


Hmm, wonder if it's just the max socket TDP for AM5. Could be AMD is giving itself some extra headroom.
 

Abwx

Lifer
Apr 2, 2011
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That s half old news set apart for the TDPs list, according to a May 27 french article 170W is the short term boost.

ZEN-4-cpu.jpg


 

soresu

Diamond Member
Dec 19, 2014
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That's refrigerant based cooling.
So is the TSMC effort.

Solid state heat conduction for 3D stacks sounds cool and simple in theory.

But in practice it simply isn't viable for logic stacks without some radically new tech, parhaps thermal transistors which are still largely at the lab research phase IIRC.

The main problem is that the heat won't just move in the right direction without some kind of external force acting upon it, as with liquid current, or the process through which heat pipes work (wicking?) - though I'm not even certain a heat pipe could work adequately at that scale.

Micro fluidic silicon via channels are a lot more advanced than anything currently in the cooling market that does not cost an arm and a leg to operate.

It wouldn't surprise me if all in one MF pump/reservoir/radiator coolers could be created which just directly attach to the socket as current air coolers do - and likely somewhat more compact than current AIO models, at least for SKUs closer to current TDPs rather than 4-8 hi stacks of logic, or something with similarly insane thermal density.

I have to say that I've never been a fan of liquid cooling before, but this does make me hope for a future with it fully integrated at chip level.

At least until some near perfect solid state solution arrives in the future, assuming that better materials/devices for logic, memory, IO and power IC's don't make cooling largely redundant by then.

Which advanced spintronic devices/materials could certainly do for logic and memory - likewise for photonics and IO. Power remains problematic though, unless graphene or some similar 2D material can handle that without significant resistance thermals in stacks.
 

eek2121

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Aug 2, 2005
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Dunno, but if the pic above is accurate then the i/o device seems quite big since TSMC s 6nm has 3x GF s 14LP density, so possibly for a basic GPU.

Probably a pre overclocked model. Anyone remember the Athlon FX-51 and similar models from back in the day?

Coincidentally, a 280mm AIO can cool a 170W CPU. without much issue. Maybe we will see 5ghz all core out of it.