Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[moinmoin]

Raphael is AM5 only...

Well yes, the names are specific for platform, dies get reused across many of them anyway (see Zeppelin, CCD etc.).

Rembrandt and/or Phoenix will be in laptops and Phoenix is in 5nm, i hope that AMD can fit more cores on it

You seriously expect a 16c monolithic APU? I consider that very farfetched.

 

[uzzi38]

Raphael is AM5 only... Rembrandt and/or Phoenix will be in laptops and Phoenix is in 5nm, i hope that AMD can fit more cores on it

It wasn't according to old slides, I don't expect AMD to have killed it off.

Pretty sure GN's shown the slide in a HW news recap or smth

 

[Mopetar]

You know we are discussing future products? You can bet that Intel will put a version of its 8+8 ADL as H series on laptops as well, TDP be damned. Currently AMD equals even H series CPUs with its APUs, but I doubt AMD will do a monolithic 16c APU to be able to do the same with ADL as well. That's where Raphael with any iGPU can slot in.

AMD wants to be clearly ahead of the competition spec wise. Intel trying to match AMD pushed more and more desktop style chips into the laptop market, so with said market and its audience getting used to those frankly absurd machines AMD is likely to follow suit now.

It's a fair assumption to assume that Intel will make such a part, but it certainly won't be cheap because it's either a separate piece of silicon developed to be that way or it's the best of the best of their full dies.

Really I don't agree with the mindset that AMD needs to beat Internet at every possible imaginable product category, no matter how niche it may be. Down that road lies defeat, mostly self-inflicted. Until Zen 3 AMD didn't have the best gaming CPUs, but they had good enough (and getting better and better) and rather than worrying about that just focused on doing what they could do best and exploiting the advantages that they had.

Intel's actions are out of AMD's control. If they want to push a crazy performance die, TDP be damned, it probably won't come off too well, just like all the other times that Intel has pushed a crazy power hungry CPU just to eke out that last bit of performance. AMD should know from when they tried it back with Bulldozer and were similarly lambasted for what was a ridiculous product.

You seriously expect a 16c monolithic APU? I consider that very farfetched.

I mean you just proposed that Intel was making one. Maybe it's different because it's a big.LITTLE design, but is it unreasonable to assume that 16 Zen 4 cores on TSMC's 5nm node take up no more space than all the cores on Intel's 10nm? Maybe they do, but certainly not so much more that it's impractical to make such a die.

I think a 16 core APU is unreasonable for other reasons, but I'm sure there are some people who would buy such an APU, even if I think it's silly. However there's also an assumption that they need 16 cores to compete with a supposed 8/8 Intel product. What if they only need 12 Zen 4 cores in order to be competitive? Before that might have seem far fetched itself, but after Zen 3 the notion that Intel would always have the better core, but AMD could just throw more of them into a product to compete is no longer a given.

 

[A///]

@A///

If Intel craps out now or at/after Raptor Lake, it's gonna get ugly. Reach for your wallet.

Ok clearly I have the wrong product charts because I was under the impression Meteor Lake (ha ha) would be coming after Alder Lake, and that posts referencing LGA1700 for both Alder and Raptor lake were simply incorrect. I've not seen the submissions Intel has made to various bodies as per referencing in rumor articles.

Though I'm a little confused by your wallet statement. Do you think demand for AMD products will increase to what we saw since they came out until about 2 months ago when supplies normalized?

 

[Ajay]

Ok clearly I have the wrong product charts because I was under the impression Meteor Lake (ha ha) would be coming after Alder Lake, and that posts referencing LGA1700 for both Alder and Raptor lake were simply incorrect. I've not seen the submissions Intel has made to various bodies as per referencing in rumor articles.

Though I'm a little confused by your wallet statement. Do you think demand for AMD products will increase to what we saw since they came out until about 2 months ago when supplies normalized?

I'd expect an increase for AMD's initial N5 offerings. They are a business, not a charity. But, we shall see.

 

[A///]

I'd expect an increase for AMD's initial N5 offerings. They are a business, not a charity. But, we shall see.

Yeah, I'm fine with this, to be honest. Today's AMD prices are cheap for what you get. AMD used to be much more expensive before Core 2 came knocking. They were at either price parity depending on the model or more expensive than the best Pentiums at the time except for their time. I remember the Athlon 64 FX outperforming the P4 EE and costing at least 200-300 more than the P4.

Without looking at any charts you can buy a 3600 used now and it would whip the life out of those processors if they could be run on a modern OS. People are really stuck on Core 2 era pricing and not thinking clearly, especially when it comes to pure clock speed or cores.

 

[jpiniero]

Really I don't agree with the mindset that AMD needs to beat Internet at every possible imaginable product category, no matter how niche it may be. Down that road lies defeat, mostly self-inflicted. Until Zen 3 AMD didn't have the best gaming CPUs, but they had good enough (and getting better and better) and rather than worrying about that just focused on doing what they could do best and exploiting the advantages that they had.

The rumors are saying that AMD is doing this. Namely that Raphael has an IGP and that there will be mobile versions up to 16 cores.

My assumption is that the APU will be 8 cores.

 

[Ajay]

The rumors are saying that AMD is doing this. Namely that Raphael has an IGP and that there will be mobile versions up to 16 cores.

My assumption is that the APU will be 8 cores.

IGP? In the IOD?

 

[jpiniero]

IGP? In the IOD?

That part is speculation but using a chiplet or something seems unlikely.

 

[jamescox]

If you have next gen IO + cores + SRAM + DRAM, + medium level graphics, that could be 1000 mm2 (especially adding DRAM)

You can't make that monolithic

I was, I believe, talking about a stacked APU for desktop or mobile, not Epyc, or anything close to the size of a discrete gpu. Where do you get 1000 mm2 from? For a high end mobile APU, which might be worth the cost of stacking, it isn’t going to be anywhere near 1000 mm2. It would be small IO base die, cpu die, maybe a single stack of HBM. That would make an excellent mobile chip.

 

[Mopetar]

The rumors are saying that AMD is doing this. Namely that Raphael has an IGP and that there will be mobile versions up to 16 cores.

My assumption is that the APU will be 8 cores.

I don't think those rumors are particularly good for various reasons. Obviously not every rumor comes to to be true and I think I've explained why I don't believe that a GPU will be included on the IO die for future products in the near term. Clearly I could just be plain wrong, but I'm expecting Zen 4 chiplets on TSMC 5nm with an IO die on GF 12LP+. I also suspect we'll get some 5nm APUs, but depending on wafer availability there could be a 6/7nm refresh as well.

As to why I think this is likely, it's a mix of available facts and what's just most likely based on what we've already seen. We already know AMD has committed to buying ~$1.6 billion in wafers from Global Foundries through 2024. An updated IO die using their 12LP+ node just seems like the most likely use of all of those wafers, which based on pricing estimates amounts to somewhere around half a million wafers. We already know that Zen 4 is using TSMC's 5nm process as well.

Beyond that I don't know what Zen 4 will look like. An 8-core chiplet seems reasonable, but they could certainly shift to 12-core chiplets as well, which would mean that they'd likely have a 12-core APU just to save on the design work. Really I don't think there's too many people who need a 12-core APU, but I'm sure they can do a lot of binning with such a part. I suspect that 12LP+ IO die will be more about taking advantage of power savings as opposed to shrinking the die or trying to squeeze in a GPU considering even a bare bones GPU is a lot more silicon than most are imagining.

 

[A///]

Most rumors are pointing towards AMD only using GloFlo on their low end Athlon products to pad out the remaining wafer agreement. Dropping down the node block on an IOD that remains relatively unchanged is useless, but it may very well be critical if the IOD gets a complete redesign and would significantly benefit from a smaller node. As far as I'm aware, Milan is already or will be using 12LP+.

 

[A///]

Beyond that I don't know what Zen 4 will look like. An 8-core chiplet seems reasonable, but they could certainly shift to 12-core chiplets as well, which would mean that they'd likely have a 12-core APU just to save on the design work. Really I don't think there's too many people who need a 12-core APU, but I'm sure they can do a lot of binning with such a part. I suspect that 12LP+ IO die will be more about taking advantage of power savings as opposed to shrinking the die or trying to squeeze in a GPU considering even a bare bones GPU is a lot more silicon than most are imagining.

Bit too early to say. No one said these were going to be the same sized cores. AMD also has plans on big.little.

 

[moinmoin]

It's a fair assumption to assume that Intel will make such a part, but it certainly won't be cheap because it's either a separate piece of silicon developed to be that way or it's the best of the best of their full dies.

What are you talking about? Are you even aware of Intel's HK lineup, which are exactly that, desktop dies in laptops, no changes otherwise? Like 9980HK is essentially 9900K, just in laptops?

I mean you just proposed that Intel was making one.

No, Intel is already putting desktop dies into laptop form factors for a couple years. I'm not proposing that Intel is changing anything about that approach, so 8+8 ADL in laptops is very close to a given. I (along others) am proposing that with Raphael AMD is following suit, and for that it needs an iGPU.

 

[Mopetar]

Honestly I haven't paid much attention to what Intel has been doing. Are the the desktop/notebook chips even different dies? I honestly don't know and can't tell from what I've been able to find online. The only information I can find (from Intel's website) is that the HK launched later and costs more and has a lower TDP and base clocks.

Also, why does someone need an iGPU for that? Anyone who legitimately wants a 16-core CPU could use a desktop CPU if they can't get an APU that will deliver that. Hell, there's a "mobile" Threadripper desktop replacement even though it's ridiculous. The people who want that much power are likely the same sort that want a powerful GPU for whatever work they're doing.

Is anyone selling a notebook with an i9 HK processor that doesn't have a high-end discrete GPU? I honestly didn't look very hard, but everything I could find had a 3080 or 3070 paired with it. That's why I think this whole idea that AMD needs an iGPU in a 16-core mobile CPU to be highly contrived.

 

[jamescox]

There are a few advantages to stack vs same die
- optimized process (as you mentioned) even node. 5nm Zen4 may have 6nm L3 V-Cache
- cost of processed SRAM wafer is likely a fraction of a price of logic wafer. So L3 on logic wafer is a lot more expensive. If you have 80 mm2 of logic and 288mm2 of L3 (see below), that cost differential may be higher than the entire cost of stacking.
- the the 8x64MB would actually not be 288mm2 on logic, non-optimized die. It may in fact be close to double the die size.
- 1, 2, 4, 8 levels high require just 2 types of die rather than 5 (base + 4) or salvaging die using less L3.
- area of core CCD + 8 levels of L3 is 80 + 8*36 = 80 + 288 = 368mm2, which could hurt yields
- vs. assembling 9 (tested) good die.
- AMD can decide late if it wants to stack any L3 and how many
- distances are actually shorter in stacked die vs. monolithic. The height of each layer is extremely thin.

The advantages of stacking IMO could completely outweigh the costs. Additionally, stacking turns an insane product spec - say Epyc with 2 GB of L3 into something quite feasible and affordable.

I have only seen up to 4 layers of cache, but that may be a Milan-x limitation, rather than a Zen 4 limitation. I believe TSMC supports up to 12 layers though. I don’t know if they can test the die before stacking them. With HBM, they have “known good die stacks” to start with. Something can still go wrong in the bonding process through.

The cpu die with cache chips might be much more expensive since you are adding another set of steps where something can go wrong and reduce yield. I think only the very high end HPC products will get 4 layers. Those that end up in the consumer market as Ryzen parts might actually be salvage and/or single layer parts. If something goes wrong with a 4 layer stack, you might still be able to use it as a 2 layer, single layer, or no stacking if all of the cache die are unusable. They might have a specific single layer part for high end, but not ridiculously expensive Epyc processors. If something goes wrong with the single layer part, then they can probably still sell it as an Epyc or Ryzen without stacked cache enabled. There should be lots of opportunities for salvage, but there is still a huge amount of silicon going into these things.

If something like a GB (or 2) of SRAM on one package actually exists, I doubt it will be classified as “affordable” by most people. For certain HPC applications, maybe big database servers and other things with expensive, per core licensing, it may be well worth the cost, but probably still not “affordable”. We seem to be going to get some threadrippers and Ryzen parts with a single layer, but those aren’t going to be cheap. I don’t think Intel will have anything close; this isn’t doable on a monolithic die. Even if intel has HBM and AMD doesn’t, HBM is good for bandwidth, but it is still DRAM with DRAM-like latencies.

 

[A///]

I have only seen up to 4 layers of cache, but that may be a Milan-x limitation, rather than a Zen 4 limitation. I believe TSMC supports up to 12 layers though. I don’t know if they can test the die before stacking them. With HBM, they have “known good die stacks” to start with. Something can still go wrong in the bonding process through.

The cpu die with cache chips might be much more expensive since you are adding another set of steps where something can go wrong and reduce yield. I think only the very high end HPC products will get 4 layers. Those that end up in the consumer market as Ryzen parts might actually be salvage and/or single layer parts. If something goes wrong with a 4 layer stack, you might still be able to use it as a 2 layer, single layer, or no stacking if all of the cache die are unusable. They might have a specific single layer part for high end, but not ridiculously expensive Epyc processors. If something goes wrong with the single layer part, then they can probably still sell it as an Epyc or Ryzen without stacked cache enabled. There should be lots of opportunities for salvage, but there is still a huge amount of silicon going into these things.

If something like a GB (or 2) of SRAM on one package actually exists, I doubt it will be classified as “affordable” by most people. For certain HPC applications, maybe big database servers and other things with expensive, per core licensing, it may be well worth the cost, but probably still not “affordable”. We seem to be going to get some threadrippers and Ryzen parts with a single layer, but those aren’t going to be cheap. I don’t think Intel will have anything close; this isn’t doable on a monolithic die. Even if intel has HBM and AMD doesn’t, HBM is good for bandwidth, but it is still DRAM with DRAM-like latencies.

Chances are they're testing out 4 and over layered stacks and have been for a while. I mean why not dogfood your own future product, especially when it would net you hundreds of million if not billions.

I was a little surprised Alderlake would be monolothic. Honestly though for the longest time it was going to be a chiplet based processor. I was only corrected on this back in December. The way Intel talked about their next-gen hardware you'd think it was the second coming of you know what.

Frankly, I don't have too much faith in Alderlake or even whatever they decide to push out after it. No point in getting over excited over "leaks" which are merely extrapolated results based on a dodgy number. Not sure when Intel decides to shove Alderlake out, but we should see better leaks weeks before its launch. I hope we do.

 

[DrMrLordX]

Raphael is on AM5 socket so it's only for desktop not for laptop, after Cezanne for laptop there will be Rembrandt and Phoenix

Tell that to the posters speculating that AMD will be using Raphael variants in laptops.

Renoir is power efficient, like Cezanne so i don't understand. Which laptop are-you talking about ?

All of them. In order for my commentary to make any sense, you have to go as far back as mobile Kaveri, but it's the same story every generation: AMD sells APUs with competent iGPUs and OEMs underspec cooling, lower cTDP for the APU, and include a dGPU. Eventually AMD is going to learn to provide monolithic APUs with the majority of their power budget committed to the CPU cores, providing only a tiny iGPU similar to what Intel often does with their mobile offerings (TigerLake-U notwithstanding).

I suspect this means exactly what has been leaked: Raphael will have an iGPU, and there will be no “G” parts this time around.

There will eventually. They'll just be based on Rembrandt, and then later Phoenix.

Ok clearly I have the wrong product charts because I was under the impression Meteor Lake (ha ha) would be coming after Alder Lake, and that posts referencing LGA1700 for both Alder and Raptor lake were simply incorrect. I've not seen the submissions Intel has made to various bodies as per referencing in rumor articles.

Though I'm a little confused by your wallet statement. Do you think demand for AMD products will increase to what we saw since they came out until about 2 months ago when supplies normalized?

Yes Meteor Lake is coming after both Alder Lake and Raptor Lake, but there's no indication that Intel will be able to produce many of them or even sell them outside of the mobile market. Meteor Lake definitely doesn't look like it's going to save their desktop business, must less DCG, where it'll be competing with Granite Rapids for wafers. Absent help from TSMC, Intel won't have enough 7nm wafers for even Granite Rapids to be a serious presence in the enterprise market, much less a full-frontal onslaught of mobile + desktop Meteor Lake. There is the very real possibility that Intel will be stuck on Raptor Lake and Sapphire Rapids for awhile until they can get their foundry mess in order. That will allow AMD to raise prices regardless of relative demand since they'll have Zen4 and Zen5 products with no real answer from Intel.

 

[Thibsie]

I'm not sure Raphael being on AM5 excludes the possibility of an FP4 version (relevancy is another problem).
Renoir exists both on AM4 and FP3 AFAICT.

 

[DisEnchantment]

I'm not sure Raphael being on AM5 excludes the possibility of an FP4 version (relevancy is another problem).

You mean AMD will offer Raphael DT dies on laptop packages, i.e. the CCD and IOD will be packaged in FP7/FP6? or the LGA1728 would be used on the mobile form factor?
I remembered someone on here said Mobile SoCs are low margin and price sensitive which packaging 1x cIOD and at least 1x CCD won't help (that too assuming cIOD has an iGPU, if not even more concerns)
Won't they also want LPDDR5 as well, or the cIOD supports LPDDR5?
RMB for sure can be packaged in AM5.

One thing I don't like is that their Mobile roadmap seems to be on a node behind DT. Exact opposite of what I would expect, but I guess there is already an upper bound which the likes of Lenovo are willing to pay for their Laptop PCs. Too many parties involved in the BOM costs.
The Mobile Form factor is the one that needs any possible efficiency improvements.

Update:
Now I found the GN leak

AMD Raphael (Zen4 & AM5) presentation from March 2020 leaks out - VideoCardz.com

AMD Raphael AM5 details leak out Gamers Nexus revealed alleged AMD internal slides they had received back in March 2020. Those slides feature details on AMD’s yet unannounced product codenamed Raphael, which is to be the first Zen4 based desktop CPUs series. The media has decided to withhold...

videocardz.com

Looks like I am not the target demographic for such devices. I am in need of M1 like SoCs which can deliver enough performance for running engineering apps on thin and light devices. Will be a long wait for Phoenix/STP.
I don't work on the engineering tasks all day long, but I need to open engineering applications to discuss with teams regularly.

 

[DrMrLordX]

One thing I don't like is that their Mobile roadmap seems to be on a node behind DT. Exact opposite of what I would expect

AMD still focuses primarily on server/workstation. Desktop inherits the CCDs from those efforts. Mobile can't really use those CCDs effectively so they have to do different designs (up to this point, monolithic).

 

[coercitiv]

You mean AMD will offer Raphael DT dies on laptop packages, i.e. the CCD and IOD will be packaged in FP7/FP6? or the LGA1728 would be used on the mobile form factor?
I remembered someone on here said Mobile SoCs are low margin and price sensitive which packaging 1x cIOD and at least 1x CCD won't help (that too assuming cIOD has an iGPU, if not even more concerns)

One thing I don't like is that their Mobile roadmap seems to be on a node behind DT. Exact opposite of what I would expect, but I guess there is already an upper bound which the likes of Lenovo are willing to pay for their Laptop PCs.

I believe they're talking about high-end gaming machines, packaging cost won't be an issue there. I couldn't follow the discussion here properly since too many voices equate their needs to the entire mobile sector requirements, generating a lot of interference, but AMD introducing their chiplet based products in the upper range of gaming/productivity oriented "mobile" products would help them compete more easily since A) chiplets will launch first over monolithic APUs and B) total available volume for the mobile market would increase.

 

[jamescox]

AMD still focuses primarily on server/workstation. Desktop inherits the CCDs from those efforts. Mobile can't really use those CCDs effectively so they have to do different designs (up to this point, monolithic).

Some TSMC stacking tech, like SoIC, mostly remove the power penalties for using multiple die, so it would be technologically possible (from a power consumption perspective) to make a stacked APU, perhaps with base IO die and cpu/gpu/memory chiplets stacked on top. It just might not be economically feasible to do that vs. a monolithic APU. If they are going to make all of their chiplets to be stacked rather than BGA package mounted, then they have to use stacking everywhere or do two different versions of the chiplet, one for stacking and one for BGA packaging.

The main performance bottleneck being the memory, a monolithic APU with some HBM2e connected via embedded silicon bridge would perform very, very well without using any other stacking. It might be lower power if the HBM is used as a cache for the whole APU to reduce power needed to communicate with off package memory. I kind of doubt that AMD will move to a “stacking only” chiplet with Zen 4, so monolithic APUs will probably be around for a while. Perhaps everything will be stacked with Zen 5.

 

[jamescox]

Chances are they're testing out 4 and over layered stacks and have been for a while. I mean why not dogfood your own future product, especially when it would net you hundreds of million if not billions.

I was a little surprised Alderlake would be monolothic. Honestly though for the longest time it was going to be a chiplet based processor. I was only corrected on this back in December. The way Intel talked about their next-gen hardware you'd think it was the second coming of you know what.

Frankly, I don't have too much faith in Alderlake or even whatever they decide to push out after it. No point in getting over excited over "leaks" which are merely extrapolated results based on a dodgy number. Not sure when Intel decides to shove Alderlake out, but we should see better leaks weeks before its launch. I hope we do.

They could be testing out higher stacks of things, but keep in mind that the base die has to support connectivity to a specific number of stacks. Zen 3 is likely designed to support a maximum of 4 layers of cache die. HBM has similar limitations with the stacked die supporting pass-through for a limited number of layers. It takes die area for TSVs to support connection to each layer, so going from 4 to 12 might not be trivial. TSMC supposedly has the pitch down to 0.9 microns which is significantly smaller than any micro-solder ball tech, but that is still 900 nm, so tens of thousands of TSVs will still take some area. You also get a higher probability of bonding failure, so they often are not going to use the max except for extremely high end devices. With AMD’s one chiplet for many products strategy, we are likely to only see a limited height stack, not the max TSMC supports.

 

[zir_blazer]

Update:
Now I found the GN leak

View attachment 47425

I find than the GPU being on the IOD is a rather... interesing choice. The other option was making APUs out of IOD + CPU + GPU dies, but that would make them dramatically more expensive, so not precisely a good idea for otherwise budget products. With the GPU on the IOD they could manage to make APUs with just IOD and CPU dies, yet it will still be behind monolithic APUs in power consumption, so I don't think that it is intended for Mobile, but maybe such lineup could go entirely for Desktop or even Server.

I recall some stories about the early Intel Chipset IGPs (Pre-Clarkdale and Sandy Bridge) where the Chipset die size and the Chipset package had to be of a minimum size in order to fit all the I/O pins required for platform connectivity. This made the Chipset dies to be way bigger than the actual logic than would be contained in them, which gave some sizeable spare space to add features that didn't required extra I/O. Typically, Intel made use of that spare space to put a bigger GPU (Which still sucked).
It may be possible than the IOD GPUs are behind monolithic APUs in both assigned die space and performance characteristics since it will be a sort of second class citizen to make use of otherwise empty leftovers, and it will be behind in process technology (All this matching the "entry level performance" claim). Seems like a product that was made intending to make all Processors usable without a dGPU, which is not a bad idea giving the current situation.


Oh, I will love it if they go for 32 PCIe Lanes. Was dissapointed than Zen had them but AM4 castrated them to 24. 32 gives far more expansion choices. May even be a good idea to drop the Chipset, you aren't as likely to require PCIe fanout. But it requires to have enough USBs, around 8 instead of AM4 4.