Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[eek2121]

If im going to be honest, it just looks like a way to workaround the lack of avalible memory on a console, as sharing 16GB for GPU+CPU, and im petty sure the S.O is reserving some of it, thats looks really bad looking forward. So being able to load assets directly from a very fast storage whiout having to go to ram first it is really usefull in those cases. BUUUUUT here is the thing, ram is still A LOT FASTER, i dont see a good reason for stop using ram as a another cache in the middle, unless you are on a console and it is either RAM or VRAM... and you want it to be VRAM for assets.

On PC, i dont think it will be very usefull, and the fact you need PCI-E 4, with a PCI-E 4 gpu and a PCI-E 4 NVME... yeah no.

There are other things developers will be able to do that they can’t do now. On mobile so I don’t want to get into it, but the initial implementations will probably suck, and then you will get that killer game that makes it work.

 

[eek2121]

Curious, given the sudden influx of AMD related leaks, I wonder if we are going to see a preview of Raphael and Milan-X for Computex...

 

[LightningZ71]

I, for one, welcome the extra PCIe channels. If they use them for extra bandwidth between the chipset and the CPU, that's a good thing, especially with the proliferation of 10Gbe and USB4 ports that are coming in the future. While it likely won't mean any extra lanes on the "X670" chipset, possibly, it will certainly help with keeping the link bandwidth contention under control in high traffic scenarios. Being able to have two PCIe 4.0 NVME drives on the chipset with minimal bus congestion at the chipset is a good thing.

 

[DisEnchantment]

It has many interesting dibits. One is that AMD might actually end up doing some ARM solutions when it's a good fit for some customers (which was probably quite obvious anyhow).
If you squint really hard (or "want to believe" ) they are also hinting of having different archs for different sweetspots (e.g. how Arm has X1 for maximum performance at a cost of area and A78 for optimized perf/watt per transistor)

You could already say, with some certainty, that a huge chunk of AMD's portfolio will be based on arm by year end. (Deal already approved in US)
All of Xilinx's ACAP are supported by arm cores.
Azure is one of the key Xilinx customers in DC/HPC and they are very interested in SmartNICs and ACAPs. And as you can guess, AMD would be more than happy to do a special super duper custom secret sauce arm based SoC for MS.

Current research indicates FPGAs to continue to gain traction for inferencing in the DC

SoC-Driven Inference Datacenters Becoming New Reality - The Next Platform

The mighty SoC is coming for the datacenter with inference as a prime target, especially given cost and power limitations. With multiple form factors stretching from edge to server, any company that provide a seamless jump from devices in the field to large-scale datacenter processing is ready...

www.nextplatform.com

Xilinx Keeps Pushing Programmable Logic As It Awaits AMD Takeover - The Next Platform

The top brass at FPGA maker Xilinx are not hosting calls with Wall Street because of the pending $35 billion acquisition of the company by AMD, so we are left to get our own insight out of the financial report and accompanying statement that Xilinx has released for its latest quarterly results...

www.nextplatform.com

Should come as no surprise that Lisa keeps mentioning that ARM is a partner.

 

[moinmoin]

Should come as no surprise that Lisa keeps mentioning that ARM is a partner.

Bears repeating that AMD has an ARM architectural license (since 2012), all Zen chips already include an ARM core, and implement ARM's TrustZone. Though Xilinx certainly will add even more obvious ARM related competency to the combined company.

 

[andermans]

Bears repeating that AMD has an ARM architectural license (since 2012), all Zen chips already include an ARM core, and implement ARM's TrustZone. Though Xilinx certainly will add even more obvious ARM related competency to the combined company.

What is the scope of such a license? Does it cover new architecture extensions (like AArch64 or ARMv9)?

 

[Ajay]

What is the scope of such a license? Does it cover new architecture extensions (like AArch64 or ARMv9)?

It doesn't matter. ARM will be happy to extend the license, for a modest fee

 

[xilli_fiberbit]

It seems to be Genoa-X :

https://twitter.com/x/status/1397530489326641152

128 Cores, 16 CCDs, 12-Channel DDR5-5200, Die Sizes

I don't know why it's called too Milan-X :

https://twitter.com/x/status/1397152544678457347

Milan-X aka Milan-X(3D). Genesis IO-die with stacked chiplets

 

[jpiniero]

It seems to be Genoa-X :

https://twitter.com/x/status/1397530489326641152

128 Cores, 16 CCDs, 12-Channel DDR5-5200, Die Sizes

Should put an Adored warning at least.

 

[uzzi38]

It seems to be Genoa-X :

https://twitter.com/x/status/1397530489326641152

128 Cores, 16 CCDs, 12-Channel DDR5-5200, Die Sizes

I don't know why it's called too Milan-X :

https://twitter.com/x/status/1397152544678457347

Milan-X aka Milan-X(3D). Genesis IO-die with stacked chiplets

https://twitter.com/ExecuFix/status/1397535849173106693?s=19

It's not Genoa-X

 

[zir_blazer]

I, for one, welcome the extra PCIe channels. If they use them for extra bandwidth between the chipset and the CPU, that's a good thing, especially with the proliferation of 10Gbe and USB4 ports that are coming in the future. While it likely won't mean any extra lanes on the "X670" chipset, possibly, it will certainly help with keeping the link bandwidth contention under control in high traffic scenarios. Being able to have two PCIe 4.0 NVME drives on the chipset with minimal bus congestion at the chipset is a good thing.

Given the fact that even the original Zen had 4 10G MACs builtin and that AM4 castrated the full Zen potential (It had 32 PCIe Lanes whereas AM4 only exposes 24. Zen could also use 8 for SATA instead of only 2. Did a Thread about Zen capabilities), I'm not impressed. 32 PCIe Lanes was a beautiful sweet spot.
Using the Chipset lanes is inferior to wiring things directly to the Processor anyways, so I don't see two NVMe SSDs on the Chipset a good thing since it is still a hop further away. Actually, one of the reasons why I want a big SoC (And with Chiplets it is easy to do, just look at Matisse and Vermeer having a Chipset die on the CPU package) is to say the discrete Chipset goodbye. I think that AMD could use a bigger socket as baseline that could fully drive a mITX and even mATX Motherboard then an optional Chipset for full fledged ATX ones if you want to fanout for more, smaller PCIe Ports that can be multiplexed because they don't use concurrent bandwidth, and more USB Ports.

 

[Gideon]

Interesting, but looks suspiciois to me:

AMD Ryzen 8000 series with Zen5 architecture allegedly codenamed Granite Ridge - VideoCardz.com

AMD Zen5 CPU codenamed Granite Ridge A new leak allegedly confirms the codename of the Ryzen 8000 series. A successor to Raphael is Granite Ridge, a leak from itacg (Weibo) appears to suggest. This is a new codename that denotes Zen5 architecture product, following Strix Point which is an APU...

videocardz.com

I find the zen5 + zen4 part odd. If zen4 is the best Big Core they have for 2022 it certainly can't be the little core of 2023, right?

 

[uzzi38]

Interesting, but looks suspiciois to me:

AMD Ryzen 8000 series with Zen5 architecture allegedly codenamed Granite Ridge - VideoCardz.com

AMD Zen5 CPU codenamed Granite Ridge A new leak allegedly confirms the codename of the Ryzen 8000 series. A successor to Raphael is Granite Ridge, a leak from itacg (Weibo) appears to suggest. This is a new codename that denotes Zen5 architecture product, following Strix Point which is an APU...

videocardz.com

I find the zen5 + zen4 part odd. If zen4 is the best Big Core they have for 2022 it certainly can't be the little core of 2023, right?

It'll be the basis for the little, but some modifications made for area reasons. ISA support is supposedly the same between both cores.

 

[Gideon]

It'll be the basis for the little, but some modifications made for area reasons. ISA support is supposedly the same between both cores.

This also hints that Zen5 is significantly larger architecture. Sort of X1 vs A78. I hoped AMD would already do that with Zen4, but it will probably be a jump more akin to Zen 2 and 3 (with new instructions and a 15-20% IPC gain)

New Vector/ ML instruction support should be all but guaranteed. No way AMD will ride to Zen 5 with AVX2 only (which they already support since Excavator)

 

[Asterox]

Let's say Zen 4 has 25% higher IPC, do we need more then 16 Big cores on Mainstream Desktop.

Up to 24 Cores on AM5 socket, ok as top model if there is a need(competition from Intel) for such a processor.

 

[DisEnchantment]

This also hints that Zen5 is significantly larger architecture. Sort of X1 vs A78. I hoped AMD would already do that with Zen4, but it will probably be a jump more akin to Zen 2 and 3 (with new instructions and a 15-20% IPC gain)

New Vector/ ML instruction support should be all but guaranteed. No way AMD will ride to Zen 5 with AVX2 only (which they already support since Excavator)

I am not sure by the time Zen5 comes the CPU is going to be same as we know today. Especially in the DC.
I think was it Forrest Norrod or Mark Papermaster who said this already, that the notion of doing updates to the current CPU architecture is not going to hold true in the long run, that we should expect AMD to address diversifying workloads not with current x86 cores but rather a more heterogenous architecture?
When I find the interview will update.

Also, is there an option to hide posts without ignoring? Am getting weary about leaks lately. There is just too many and basically covers all dimesions in all the performance axes

 

[DrMrLordX]

Q3 2022? That better not be true.

 

[Shivansps]

If there are 3 chiplets on Raphael, i would guess one of them could be a RDNA3 chiplet.

 

[mikk]

Q3 2022? That better not be true.

Earlier than expected if true, the last rumors pointed towards late 2022. It's a bit early to predict anyways, a lot can happen in the next months.

 

[uzzi38]

Let's say Zen 4 has 25% higher IPC, do we need more then 16 Big cores on Mainstream Desktop.

Up to 24 Cores on AM5 socket, ok as top model if there is a need(competition from Intel) for such a processor.

View attachment 44959

He's out on line 1.

Disregard.

 

[exquisitechar]

He's out on line 1.

Disregard.

Oh, you already know about it? I suppose his figure is too high.

There's some other things that seem off in that video too.

 

[uzzi38]

Oh, you already know about it? I suppose his figure is too high.

There's some other things that seem off in that video too.

No I mean Zen 4 CCDs have taped out. It is very much design complete and silicon exists already.

 

[exquisitechar]

No I mean Zen 4 CCDs have taped out.

Didn't notice the image at first. Yeah, that seems wrong.

Has MLID ever even gotten anything AMD related right that wasn't already leaked by someone before him?

 

[uzzi38]

Didn't notice the image at first. Yeah, that seems wrong.

Has MLID ever even gotten anything AMD related right that wasn't already leaked by someone before him?

I don't know, and to be frank, I don't entirely care. He's said enough bollocks for me to know that he's more than happy to either make stuff up or trust things from absolutely anyone.

You guys remember this one? I know who made it up. Hell a couple of things on their I contributed to. It was total BS designed to see who would take the bait without attempting to verify their sources, and MLID posted it in a video within just hours of receiving it.

 

[exquisitechar]

I don't know, and to be frank, I don't entirely care. He's said enough bollocks for me to know that he's more than happy to either make stuff up or trust things from absolutely anyone.

You guys remember this one? I know who made it up. Hell a couple of things on their I contributed to. It was total BS designed to see who would take the bait without attempting to verify their sources, and MLID posted it in a video within just hours of receiving it.

I remember that. Well, in any case, his Zen 4 leak is bunk.