My latest theory on the CPU cores of Mi300 is that the graphical representation is probably incorrect and it is 3 Zen4 chiplets of 8 cores each.It is very reasonable to assume, that they might make it happen (twice the cores on the same area. I also suspect them to use another IO - either full on SoIC or InFO-RDL.
Pure speculation:
I measured the block on the MI300 render that I suspect to be the 16c Zen4c CCD and it nicely fits the area bill (see the Zen5 thread around two weeks back, as ATM I am just too lazy).
It would require the least amount of changes from the existing Zen 4 chiplet.