Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[nicalandia]

Zen started out with 4 cores per CCX until Zen 3 increased it to 8 cores. Zen 4 seems to use the same config. Zen 4c in Bergamo may change that again, depending on the amount of CCDs and CCXs per CCD.

Bergamo will sure will use two CCDs stiched together to form a single 16 core die.

 

[Timmah!]

Based on todays info about those voltage controls, can anyone tell if v-cachw will have separate control this time around to perhaps alleviate the issues with 5800x3d?

 

[moinmoin]

Bergamo will sure will use two CCDs stiched together to form a single 16 core die.

Stitched together? Why not monolithic? Otherwise it's not a single die. Also does that make it one or two CCXs (with respective unified or separate L3$)?

 

[inf64]

Was browsing the IEEE Micro and found a reference to the article called "What Made Us Stronger: An Inside Look Back at the History of AMD Microprocessor Development".
Had some luck and thanks to Retired Engineer on Twitter, found a printscreen of the most interesting part: Zen development:

https://twitter.com/x/status/1467180596090658823

So the Zen 3 IPC goal was (internally) 30% over Zen 1, done by the former K12 team. Zen 1 goal over Excavator was 40%. Both were labeled as "clean sheet" designs.
Zen 3 effectively got us 1.03 (Zen +) x 1.15 (Zen 2) x 1.19 (Zen 3) =1.4 or 40% over Zen 1.

Zen 5 is also called "clean sheet" design by AMD, and judging from the above, the goal should be at minimum 30% over Zen 3 (previous clean sheet design). If they were ambitious, they might have targeted 40% and just maybe overshot it. Hint towards that outcome is with how much enthusiasm Mike Clark talked about Zen 5. This could put Zen 5 at 30% better IPC than Zen 4. The former K12 team should also developed the Zen 5 core, if the cadence remained the same as before.

Zen 4 will turn out to be great due to a combination of medium sized IPC increase (~10%) and very big jump in effective clock speeds (and cpu core count for select markets). 2024 can't come soon enough!

 

[inf64]

Found an interesting Genoa ES Geekbench5 score (thanks to a twitter thread ).

Old Genoa ES 32C leak from March 2022, Geekbench 5.4.4 on Linux (max boost 3430Mhz) : https://browser.geekbench.com/v5/cpu/13894822
ST score 1126

Newer Genoa ES 32C leak from May 2022, Geekbench 5.4.4 on Linux (max boost 3430Mhz) : https://browser.geekbench.com/v5/cpu/14856290
ST score 1404

Compare with 5950X running at stock, Geekbench 5.4.4 on Linux ( max boost 5000Mhz) : https://browser.geekbench.com/v5/cpu/15913819
ST score 1725

According to above, Zen 4 @ 5.7Ghz max boost should score 1404 x 5.7 / 3.43 ~= 2333 pts on Linux. That is around 2333/1725= 35% higher ST score vs stock 5950X (5Ghz max boost). Per clock, that is (1404 x 5/3.43) / 1725 ~= 1.186 or 18.6%. This is considerably higher than what AMD stated in their average number that is a geo-mean of R23 ST, GB5 ST and SPEC_1T. Either the R23 is weakest of the bunch, dragging the average down along with SPEC, and Geekbench is an outlier, OR the newer leaked Genoa ES result is some sort of an outlier.

I guess it's possible we have this kind of distribution of IPC per benchmark that fits the ~10% average:
R23 1T => 5% higher IPC
SPEC_1T => 9% higher IPC
Geekbench5 1T => 18% higher IPC
------------------------------------------------------------
Geo-mean is ~10%

Edit:

Here is the slowest clocking Zen 3 part running Linux,(Ryzen 5 5500, @ 4.2Ghz in ST) vs the Genoa ES : https://browser.geekbench.com/v5/cpu/compare/15906141?baseline=14856290

The clock difference is ~23.6% in favor of Zen 3 core, have that in mind when looking at individual ST subscores. If we eliminate the outliers, it looks like the IPC difference is varying between 5 and 12%.

 

[biostud]

I think we should find a better term than IPC as at basically refers to something else, than we we are actually talking about. What we typically compare are software performance ST and MT and gaming performance, and as we know these also scores differently with different memory speeds and cache size, when paired with the same "core".

 

[LightningZ71]

Found an interesting Genoa ES Geekbench5 score (thanks to a twitter thread ).

Old Genoa ES 32C leak from March 2022, Geekbench 5.4.4 on Linux (max boost 3430Mhz) : https://browser.geekbench.com/v5/cpu/13894822
ST score 1126

Newer Genoa ES 32C leak from May 2022, Geekbench 5.4.4 on Linux (max boost 3430Mhz) : https://browser.geekbench.com/v5/cpu/14856290
ST score 1404

Compare with 5950X running at stock, Geekbench 5.4.4 on Linux ( max boost 5000Mhz) : https://browser.geekbench.com/v5/cpu/15913819
ST score 1725

According to above, Zen 4 @ 5.7Ghz max boost should score 1404 x 5.7 / 3.43 ~= 2333 pts on Linux. That is around 2333/1725= 35% higher ST score vs stock 5950X (5Ghz max boost). Per clock, that is (1404 x 5/3.43) / 1725 ~= 1.186 or 18.6%. This is considerably higher than what AMD stated in their average number that is a geo-mean of R23 ST, GB5 ST and SPEC_1T. Either the R23 is weakest of the bunch, dragging the average down along with SPEC, and Geekbench is an outlier, OR the newer leaked Genoa ES result is some sort of an outlier.

I guess it's possible we have this kind of distribution of IPC per benchmark that fits the ~10% average:
R23 1T => 5% higher IPC
SPEC_1T => 9% higher IPC
Geekbench5 1T => 18% higher IPC
------------------------------------------------------------
Geo-mean is ~10%

Edit:

Here is the slowest clocking Zen 3 part running Linux,(Ryzen 5 5500, @ 4.2Ghz in ST) vs the Genoa ES : https://browser.geekbench.com/v5/cpu/compare/15906141?baseline=14856290

The clock difference is ~23.6% in favor of Zen 3 core, have that in mind when looking at individual ST subscores. If we eliminate the outliers, it looks like the IPC difference is varying between 5 and 12%.

Please note that the 5500 has only 16MB of L3, being based on Cezanne and not the Zen3 CCD of the 5XXX series desktop processors. Your better bet is the 5600 (nonX).

 

[tamz_msc]

I would rather compare runs with frequencies as close as possible to avoid scaling effects creeping into the comparison. So, here's an EPYC 7763 running at 3.5 GHz boost against this engineering sample running at 3.4 GHz boost.

Looking at the AES scores, it is clear that AVX-512 is playing a part in the ES, but otherwise, the scores are almost identical, for both integer and FP. We are looking at a performance per clock uplift of just over 3%.

 

[Joe NYC]

Was browsing the IEEE Micro and found a reference to the article called "What Made Us Stronger: An Inside Look Back at the History of AMD Microprocessor Development".
Had some luck and thanks to Retired Engineer on Twitter, found a printscreen of the most interesting part: Zen development:

https://twitter.com/x/status/1467180596090658823

View attachment 65650

So the Zen 3 IPC goal was (internally) 30% over Zen 1, done by the former K12 team. Zen 1 goal over Excavator was 40%. Both were labeled as "clean sheet" designs.
Zen 3 effectively got us 1.03 (Zen +) x 1.15 (Zen 2) x 1.19 (Zen 3) =1.4 or 40% over Zen 1.

Zen 5 is also called "clean sheet" design by AMD, and judging from the above, the goal should be at minimum 30% over Zen 3 (previous clean sheet design). If they were ambitious, they might have targeted 40% and just maybe overshot it. Hint towards that outcome is with how much enthusiasm Mike Clark talked about Zen 5. This could put Zen 5 at 30% better IPC than Zen 4. The former K12 team should also developed the Zen 5 core, if the cadence remained the same as before.

Zen 4 will turn out to be great due to a combination of medium sized IPC increase (~10%) and very big jump in effective clock speeds (and cpu core count for select markets). 2024 can't come soon enough!

BTW, RetiredEngineer also found some info supporting the theory that Zen3 team stayed intact to develop Zen4.

Implying Zen5 team has been in development by a separate team.

 

[inf64]

Please note that the 5500 has only 16MB of L3, being based on Cezanne and not the Zen3 CCD of the 5XXX series desktop processors. Your better bet is the 5600 (nonX).

I found a few Linux results for a few Ryzen 5600 systems and the IPC in ST test is between 10 and 12% in favor of the Genoa ES.

 

[inf64]

BTW, RetiredEngineer also found some info supporting the theory that Zen3 team stayed intact to develop Zen4.

Implying Zen5 team has been in development by a separate team.

Yes, interesting indeed :

https://twitter.com/x/status/1544149696888811520

It's possible that Mike Clark is the chief architect of Zen 5? He headed the Zen 1 design team, so if the above is true, he was in charge of Zen 5 as well.

Edit:

Because the Zen 1 team headed Zen 2 development as well, it's logical the releases were 2 years apart (we had a minor refresh in the form of Zen 1+ in between).

This explains why we have a gap of 2 years between Zen 3 and Zen 4 - the same team was in charge of development of both of these cores so that explains the similar 2 year gap. If this was to happen again, the Zen 6 core should arrive in 2026 which seems very far away. Hopefully Zen 5 will be a monster design ready to go head to head with intel's Royal Core.

 

[Hans Gruber]

BTW, RetiredEngineer also found some info supporting the theory that Zen3 team stayed intact to develop Zen4.

Implying Zen5 team has been in development by a separate team.

When Ryzen (Zen1) was announced/released. They had the entire Zen architecture mapped out through Zen 4 back in (2017). Zen 5 is a new roadmap.

 

[Zucker2k]

BTW, RetiredEngineer also found some info supporting the theory that Zen3 team stayed intact to develop Zen4.

Implying Zen5 team has been in development by a separate team.

That's interesting because it'll mean that the Zen 2 team is doing Zen 5. Well, the Zen 3 team proved formidable at optimization so maybe not bad at all since it'll mirror the Zen 2 -> Zen 3 cadence. Should prove interesting, if true.

 

[szrpx]

Was browsing the IEEE Micro and found a reference to the article called "What Made Us Stronger: An Inside Look Back at the History of AMD Microprocessor Development".
Had some luck and thanks to Retired Engineer on Twitter, found a printscreen of the most interesting part: Zen development:

https://twitter.com/x/status/1467180596090658823

View attachment 65650

So the Zen 3 IPC goal was (internally) 30% over Zen 1, done by the former K12 team. Zen 1 goal over Excavator was 40%. Both were labeled as "clean sheet" designs.
Zen 3 effectively got us 1.03 (Zen +) x 1.15 (Zen 2) x 1.19 (Zen 3) =1.4 or 40% over Zen 1.

Zen 5 is also called "clean sheet" design by AMD, and judging from the above, the goal should be at minimum 30% over Zen 3 (previous clean sheet design). If they were ambitious, they might have targeted 40% and just maybe overshot it. Hint towards that outcome is with how much enthusiasm Mike Clark talked about Zen 5. This could put Zen 5 at 30% better IPC than Zen 4. The former K12 team should also developed the Zen 5 core, if the cadence remained the same as before.

Zen 4 will turn out to be great due to a combination of medium sized IPC increase (~10%) and very big jump in effective clock speeds (and cpu core count for select markets). 2024 can't come soon enough!

Edit: Ignore me, restating what yall said.

 

[Joe NYC]

That's interesting because it'll mean that the Zen 2 team is doing Zen 5. Well, the Zen 3 team proved formidable at optimization so maybe not bad at all since it'll mirror the Zen 2 -> Zen 3 cadence. Should prove interesting, if true.

From what we know of Zen 4, it is evolutionary, optimizing parts that did not make it to Zen 3. Most likely, the same design team has another offshoot in Zen4c, after Zen4 was completed...

 

[Vope45]

Yes, interesting indeed :

https://twitter.com/x/status/1544149696888811520

It's possible that Mike Clark is the chief architect of Zen 5? He headed the Zen 1 design team, so if the above is true, he was in charge of Zen 5 as well.

Edit:

Because the Zen 1 team headed Zen 2 development as well, it's logical the releases were 2 years apart (we had a minor refresh in the form of Zen 1+ in between).

This explains why we have a gap of 2 years between Zen 3 and Zen 4 - the same team was in charge of development of both of these cores so that explains the similar 2 year gap. If this was to happen again, the Zen 6 core should arrive in 2026 which seems very far away. Hopefully Zen 5 will be a monster design ready to go head to head with intel's Royal Core.

Mike Clark works on zen 5 that's about it for the moment.

 

[NostaSeronx]

Mike Clark is Super Chief Architect/Designer/Head/Director for all of Zen architectures.
David Suggs is the Chief Architect for Zen2 and was/still is for Zen5.

Then:

Now:


First name from announcement, if you can find it, is in general the chief architect:

A new ×86 core architecture for the next generation of computing

This article consists only of a collection of slides from the author's conference presentation.

ieeexplore.ieee.org

Mike Clark => Zen1

AMD “ZEN 2”

This article consists of a collection of slides from the author's conference presentation.

ieeexplore.ieee.org

David Suggs => Zen2

Next Generation “Zen 3” Core

This presentation contains forward-looking statements concerning Advanced Micro Devices, Inc. (AMD) including, but not limited to, the features, functionality, availability, timing, expectations and expected benefits of AMD future products, including Ryzen™ 5000 Series CPUs and Socket AM4, which...

ieeexplore.ieee.org

Mark Evers => Zen3

Zen4 is related to Mark Evers again, so might be him or a fellow.
Zen5 is suppose to be David Suggs, but might fall up to Mike Clark.

 

[cellarnoise]

CC

I think we should find a better term than IPC as at basically refers to something else, than we we are actually talking about. What we typically compare are software performance ST and MT and gaming performance, and as we know these also scores differently with different memory speeds and cache size, when paired with the same "core".

Agree to some degree
IPC is still a good metric but varies based on task / workload. Such as games , different games and other.

I think we need better analysis of what is true 1 or 2 thread tasks vs more to thread max per cpu. We get some of this but mainly what is likely 1t plus some 2t and then all thread analysis. With OS and other typical background crap grabbing cycles is there really a good 1 thread measure anymore and if there is does it reflect actual low thread uses?

 

[DrMrLordX]

Based on todays info about those voltage controls, can anyone tell if v-cachw will have separate control this time around to perhaps alleviate the issues with 5800x3d?

We're going to have to look at motherboard VRMs to see how many separate groupings there are. My X570 Master, for example, is 12+2. 12 for the CPU, and 2 for SoC/iGPU (irrelevant since it doesn't have a video out on the motherboard, but still, that's what would feed the iGPU if there were one).

The X670E Aorus Xtreme is 18+2+2. What's the extra group for? I have no idea. Yet.

 

[Timmah!]

We're going to have to look at motherboard VRMs to see how many separate groupings there are. My X570 Master, for example, is 12+2. 12 for the CPU, and 2 for SoC/iGPU (irrelevant since it doesn't have a video out on the motherboard, but still, that's what would feed the iGPU if there were one).

The X670E Aorus Xtreme is 18+2+2. What's the extra group for? I have no idea. Yet.

oh, thaks!

 

[biostud]

We're going to have to look at motherboard VRMs to see how many separate groupings there are. My X570 Master, for example, is 12+2. 12 for the CPU, and 2 for SoC/iGPU (irrelevant since it doesn't have a video out on the motherboard, but still, that's what would feed the iGPU if there were one).

The X670E Aorus Xtreme is 18+2+2. What's the extra group for? I have no idea. Yet.

PCIe 5.0 drives?

 

[DrMrLordX]

PCIe 5.0 drives?

Lulz

I hope those don't get their own VRM phases.

 

[Tuna-Fish]

PCIe 5.0 drives?

m.2 gets 7W of 3.3V, which is delivered directly from the PSU unless the MB is made to work with ATX12VO.

 

[Timmah!]

Slow day today - i saw crapton of RaptorLake leaks with CB/GB scores lately, would not mind similar treatment for Zen4...especially 3D versions.

 

[Hans Gruber]

Question. If the Raptor Lake 13900k has 16 big cores and 8 weak little cores. If the numbers (big performance in Cinebench and some other benchmarks) are true. We don't know the Zen 4 performance of the 7950x. The performance leaks are at 240w for the 13900k but they also have better specs in complete unlimited power guzzling 450-500w. I know Zen 4 is increasing the TDP of Zen 4 processors but I do not think Zen 4 will get anywhere near Raptor Lake power usage.

Is it possible we could see a 24core or 32core Zen 4 CPU? I have been told no. But 5nm gives more real estate on the die vs. 7nm on Zen 3. Why are we not seeing potentially higher core counts for Zen 4? It makes no sense to me. 5nm vs. 10nm for Intel.
Dr. Su said that AMD would add more cores for a core war with Intel in the past.

Lastly is AMD happy with the scaling of 5nm vs. 7nm? I think they were hoping for more performance boost with the node shrink. Then we have 3nm for Zen 5 if TSMC can pull it off. Then Intel has 7nm on whatever they release after Raptor Lake. Unlike AMD and their well defined road map. Intel scraps plans and makes new cores and designs on the fly.

If Zen 4 were released near the beginning of 2022 it would be a big win for AMD. Instead AMD is allowing Intel to catch up. I know many of you think AMD is ahead of Intel. Since Alder Lake they are behind Intel except for power efficiency. Obviously on the server side Zen 4 will totally smoke Raptor Lake.