Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[jpiniero]

Zen 4 Server with 12 DDR5 channels?

https://industrial.apacer.com/en-ww/NEWS/What-Sets-DDR5-Memory-Modules-Apart--7-Key-Specification-Differences-of-Industrial-DDR5-RDIMM

Yep. 12x8=96.

 

[igor_kavinski]

Zen 4 Server with 12 DDR5 channels?

https://industrial.apacer.com/en-ww/NEWS/What-Sets-DDR5-Memory-Modules-Apart--7-Key-Specification-Differences-of-Industrial-DDR5-RDIMM

More interesting is that Raphael is gonna start its life with DDR5-5200.



That gives Zen 4 an advantage at stock settings right off the bat.

 

[Panino Manino]

Still 2 channels...

 

[nicalandia]

Zen 4 Server with 12 DDR5 channels?

https://industrial.apacer.com/en-ww/NEWS/What-Sets-DDR5-Memory-Modules-Apart--7-Key-Specification-Differences-of-Industrial-DDR5-RDIMM

Still 2 channels...

That's been known for quite a while now(so it's old news)

"Zen 4 in Genoa (server) form supports up to 12 channels of DDR5-5200. To increase bandwidth available to a single CCD, it seems AMD has opted to add more IF links to each CCD. ‘Narrow mode’ may be a way to save even more power by disabling one of the IF links when high bandwidth isn’t required"

Also on AM5



From: https://chipsandcheese.com/2021/08/23/details-on-the-gigabyte-leak/

 

[Carfax83]

More interesting is that Raphael is gonna start its life with DDR5-5200.

View attachment 60758

That gives Zen 4 an advantage at stock settings right off the bat.

Zen 4 will be facing off against Raptor Lake on desktop which will be using DDR5 5600, so I'm not sure how that's an advantage.

I think it may have an advantage server side as Sapphire Rapids uses stock DDR5 4800.

 

[nicalandia]

Zen 4 will be facing off against Raptor Lake on desktop which will be using DDR5 5600, so I'm not sure how that's an advantage.

I think it may have an advantage server side as Sapphire Rapids uses stock DDR5 4800.

Sapphire Rapids could be on DDR6 for all we care, it will still get beat like a red-headed stepchild. This what happens when you delay your product so much and they have to fight with a cpu that your successor should have been dealing with

 

[MadRat]

Don't fret about desktop not getting the love. Memory controller is on a server-grade chipset - not the CPU - so there's that.

 

[desrever]

On desktop people just run overclocked ram anyways so the official supported spec barely matters.

 

[jamescox]

Still 2 channels...

Technically 4 DDR5 channels, 2 per DIMM. It will be a lot of bandwidth still so I don’t know if it is really that much of a limitation for most circumstances.

 

[jamescox]

This is the Zen 4 thread. we need to talk about that, Not Raptor lake.

Edit: Yes I replied once about Z690 which is Intel, but lets get back to Zen 4.

Well, RedGamingTech is talking Zen 5 rumors already, but maybe they just ran out of stuff to rehash about Zen 4. His videos are usually very low on the new info content. It is amazing how little solid information we seem to have about Zen 4. Their Zen 5 rumors are saying 16 core CCX with shared L2, larger L1 and possibly L4 cache somewhere. Possibly up to 32 cores on AM5. I am thinking that it will be built using EFB as Bergamo probably will use, so Bergamo may be the pipe cleaner for a fully stacked future. Anyway, I guess we may need a Zen 5 thread. It is a different family, so much more radical changes. Zen 4 is mostly just maximized Zen 3 on a smaller process.

 

[Markfw]

Well, RedGamingTech is talking Zen 5 rumors already, but maybe they just ran out of stuff to rehash about Zen 4. His videos are usually very low on the new info content. It is amazing how little solid information we seem to have about Zen 4. Their Zen 5 rumors are saying 16 core CCX with shared L2, larger L1 and possibly L4 cache somewhere. Possibly up to 32 cores on AM5. I am thinking that it will be built using EFB as Bergamo probably will use, so Bergamo may be the pipe cleaner for a fully stacked future. Anyway, I guess we may need a Zen 5 thread. It is a different family, so much more radical changes. Zen 4 is mostly just maximized Zen 3 on a smaller process.

If you have a source for any halfway dependable Zen 5 information, then start a thread !!

 

[jamescox]

Ryzen 6000 is using AM5 DDR5. Raptor Lake will still be able to use DDR4 on their mobile platform.


OEMs will absorb and pass on the cost to the consumers. That's how things work now with this global pandemic. I've been paying more for everything for the last couple of years. I couldn't wait and ended up getting a newer Intel platform. I'm probably not going to upgrade to Zen 4 even if it's miles ahead because the new platform will have teething problems at first, doubly so because it's AMD. Zen 5 may be ideal, but yes, I'm not expecting amazing DDR5 kits for the current "performance" kits available now which are eye-watering to say the least.

I don’t think I want an Intel space heater, especially with the summer coming and electricity prices ridiculously expensive in California. I might just get a new laptop and call it done. I wish AMD would work with someone like FrameWork to make a repairable laptop. I would want 16”+ screen size though. They mostly seem to partner with Lenovo, but they are essentially on my blacklist over security concerns. Perhaps I should just get another MacBook Pro.

 

[jamescox]

If you have a source for any halfway dependable Zen 5 information, then start a thread !!

I don’t know if RedGamingTech is “halfway dependable”. We will see if others start saying the same thing.

 

[jamescox]

Sapphire Rapids could be on DDR6 for all we care, it will still get beat like a red-headed stepchild. This what happens when you delay your product so much and they have to fight with a cpu that your successor should have been dealing with

I don’t know how Intel could be competitive. There are some differences since Intel has their own Fab. AMD has to minimize there use of advanced process nodes. That shouldn’t be quite as important to Intel. Intel’s solution still seems to involve very large chips (4x at over 400 square mm?) for possibly over 1600 mm2 total. Please correct me if I am wrong; I haven’t followed Intel that closely. We are using AMD now. A lot of Epyc processors are probably 32 core or less which means only around 300 mm2 on an advanced process and another 430 for the IO die on cheap GF process. Even an 8 chiplet device would only be around 600 mm2. The cost difference might not be that relevant due to the different fab circumstances.

 

[DisEnchantment]

If you have a source for any halfway dependable Zen 5 information, then start a thread !!

No thanks, this thread was created bsed on real information from 2019. (See first post)
Not some info cooked up in the dreams of click bait YouTubers.

These days such info is hard to come by and we don't need to start another drum beating thread based on such dreams unless there is real info (like the upcoming FAD perhaps).
At least not until this thread dies when Zen 4 launches or real info emerges

 

[jamescox]

No thanks, this thread was created bsed on real information from 2019. (See first post)
Not some info cooked up in the dreams of click bait YouTubers.

These days such info is hard to come by and we don't need to start another drum beating thread based on such dreams unless there is real info (like the upcoming FAD perhaps).
At least not until this thread dies when Zen 4 launches or real info emerges

He just popped up in my feed, supposedly with Zen 5 info. I watched some of his videos a long time ago. They are mostly rehashing the same old stuff over and over again. If there is some new bit of info, usually originating from someone else, then it is often about 2 sentences from a 20 minute video. Not recommended. I don’t know if he cooked up this supposed Zen 5 info himself or if it came from somewhere else. With how quiet AMD has managed to keep Zen 4, I don’t expect any real Zen 5 info anytime soon.

 

[Ajay]

No thanks, this thread was created bsed on real information from 2019. (See first post)
Not some info cooked up in the dreams of click bait YouTubers.

These days such info is hard to come by and we don't need to start another drum beating thread based on such dreams unless there is real info (like the upcoming FAD perhaps).
At least not until this thread dies when Zen 4 launches or real info emerges

Amen! Too speculative at this point. As we've seen, AMD and Nvidia have become very guarded and are actively suppressing leaks. Intel is crowing, because they need to right now.

 

[Mopetar]

Amen! Too speculative at this point. As we've seen, AMD and Nvidia have become very guarded and are actively suppressing leaks. Intel is crowing, because they need to right now.

I think RTG was the first to mention Infinity Cache though so he does apparently get good info. I think the problem is that he just talks about anything he gets so low signal to noise.

 

[jamescox]

I think RTG was the first to mention Infinity Cache though so he does apparently get good info. I think the problem is that he just talks about anything he gets so low signal to noise.

I don’t follow the GPUs as much, but I have been looking for any info about infinity cache. I suspect that there will be significant sharing between AMD Epyc and AMD GPUs with Bergamo possibly the first product.

 

[eek2121]

Well, RedGamingTech is talking Zen 5 rumors already, but maybe they just ran out of stuff to rehash about Zen 4. His videos are usually very low on the new info content. It is amazing how little solid information we seem to have about Zen 4. Their Zen 5 rumors are saying 16 core CCX with shared L2, larger L1 and possibly L4 cache somewhere. Possibly up to 32 cores on AM5. I am thinking that it will be built using EFB as Bergamo probably will use, so Bergamo may be the pipe cleaner for a fully stacked future. Anyway, I guess we may need a Zen 5 thread. It is a different family, so much more radical changes. Zen 4 is mostly just maximized Zen 3 on a smaller process.

If you have a source for any halfway dependable Zen 5 information, then start a thread !!

Youtubers don't leak information, they plagiarize. I can prove it. Take the supposed leaked information and plug it into a few places: twitter search, google search, and youtube search. Compare the upload date of the video to the first mention of the option. I"ve never seen a single Youtuber upload something before twitter, for instance. A couple users here claimed that someone did it, then when I pointed out the info was a year old they went silent.

Many written sites such as WCCFTech attempt to get away with it by changing content. They typically rarely get caught because archival sites have to play by the rules just like search engines do.

I could go on about this subject, however, I've seen it happening repeatedly for years and years, so...

 

[xilli_fiberbit]

Venice is allegedly the codename of EPYC with ZEN6 : https://videocardz.com/newz/amd-epyc-with-zen6-architecture-is-allegedly-codenamed-venice

 

[jamescox]

Venice is allegedly the codename of EPYC with ZEN6 : https://videocardz.com/newz/amd-epyc-with-zen6-architecture-is-allegedly-codenamed-venice

It is a bit early to be talking Zen 6; this isn’t really any information. It may not even be referred to as Zen 6. Zen 5 is supposed to be a new family, so they may actually call it something else, although “Zen” is popular, so why retire it.

HBM again. HBM is still DRAM with DRAM-like latencies. It isn’t good as a cpu cache. It is unclear how AMD would use it given the massive SRAM caches they are using. They may still go to 4 high v-cache stacks. Infinity cache chips might be L4 if used on CPUs, so where would HBM be used?

They are also pretty conservative in their speculation. I have been thinking that Bergamo will be a stacked implementation, possibly sharing infinity cache chiplet, base die, or other components with their gpu products. This seems more likely given the size of the memory interfaces on Epyc.

Genoa will have 12 channel DDR5, technically 24 32-bit channels since DDR5 is two channels per DIMM. That is a 768-bit interface with 32-bits per channel like graphics memory. I could see them possibly doing away with the quadrants in the current IO die and using a 384-bit unified memory controller (UMC) on each side of the IO die or on some stacked chip. Who knows. This would reduce latency significantly though. The internal interconnections in the current IO die is rather complicated since it is somewhat like 4 separate IO die connected together with different latencies to the four 128-bit memory controllers.

The UMC could look very much like a GPU memory interface, it would just be connected to a DDR5 PHY rather than a GDDR6 PHY, although I thought GDDR6 was QDR rather than DDR, so the graphics system may need to be 2x wider internally. Reusing some of the stacked gpu components may also allow them to put a gpu into an Epyc socket with HBM and exceptionally fast access to large amounts of DDR5. Maybe 2 gpu die plus 4 HBM on one side and 4x 16-core CPU chiplets on the other.

Anyway, I wrote a ridiculously long post late at night again, but stacking seems likely to be here with the next gen GPUs, so I would expect stacked CPUs well before Zen 6; we may get them with Zen 4 Bergamo.

 

[igor_kavinski]

stacking seems likely to be here with the next gen GPUs, so I would expect stacked CPUs well before Zen 6; we may get them with Zen 4 Bergamo.

Only thing is, stacking so far has been a bit underwhelming. Intel's Foveros based CPU wasn't a success. AMD had to disable overclocking on the 5800X3D. If stacking is the future, it will not be without its share of compromises.

 

[biostud]

Only thing is, stacking so far has been a bit underwhelming. Intel's Foveros based CPU wasn't a success. AMD had to disable overclocking on the 5800X3D. If stacking is the future, it will not be without its share of compromises.

If they manage to clock it 95% of what is achievable via overclocking, then give me extra cache any day. With the turbo boosts of modern CPUs and speeds very close to a max overclock, I really don't understand why anyone is interested in overclocking anymore. It's not like in the old days where you could boost your CPU with +30% performance. Now it's mostly single digit performance increase.

 

[igor_kavinski]

Now it's mostly single digit performance increase.

If someone is on a budget and can't afford to upgrade, even a 5% overclock is better than no overclock. With the 5800X3D, you need to have an expensive mobo for BCLK OC. It doesn't matter now but what about 5 years from now when this CPU will start getting long in the tooth? What if the user wants to OC it for eking out just a little bit more performance while they save up for their next big upgrade?