Solved! Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[DrMrLordX]

If Zen 5 is to launch in 2023, and if the plan was for it to launch on N3, it would be impacted.

Same for RDNA4.

Zen5 won't be N3. I'm guessing N4 or N4P.

 

[Joe NYC]

Zen5 won't be N3. I'm guessing N4 or N4P.

I agree with that. But the original intention could have been N3.

Unlike previous nodes, where the first implementation targeted mobile (Apple), N3s was supposed to target both mobile and HPC from the outset, so it would have accommodated also CPU and GPU.

 

[DisEnchantment]

Why? They won't be first to market on N3. Intel and Apple will be.

If N3 is not ready, Apple will stick on N5/N4 which means using same fabs used by AMD/N5 for Zen 4, that is the issue. It could already be impacting Zen4 right now.
TSMC would have seen this coming for sure, but the question is how much of F18P4/5/6 which are originally planned for N3 are they willing to move back to N5 and how fast.

 

[DrMrLordX]

If N3 is not ready, Apple will stick on N5/N4 which means using same fabs used by AMD/N5 for Zen 4, that is the issue.

Pretty sure if it gets that bad, Apple will retreat to N4, and yes that might be a future problem for AMD if TSMC can't pivot quickly enough. But I do not think it will affect Zen4.

 

[Kepler_L2]

Intel already confirmed they are using N3 GPU tiles for MTL, if that is yielding enough for them, it will also yield enough for the tiny Zen5 CCDs.

 

[jpiniero]

Intel already confirmed they are using N3 GPU tiles for MTL, if that is yielding enough for them, it will also yield enough for the tiny Zen5 CCDs.

Intel only confirmed they are using N3, not for what.

If N3 is not ready, Apple will stick on N5/N4 which means using same fabs used by AMD/N5 for Zen 4, that is the issue. It could already be impacting Zen4 right now.
TSMC would have seen this coming for sure, but the question is how much of F18P4/5/6 which are originally planned for N3 are they willing to move back to N5 and how fast.

I still don't think it's a "Not Ready" issue, more that N4P theoretically could be close enough quality wise to make N3 not worth it to Apple. But it could be worth it to AMD to stick to N3 if it means much more capacity... even if the cost means it has to be super high margin products only like Epyc.

 

[andermans]

Intel only confirmed they are using N3, not for what.



I still don't think it's a "Not Ready" issue, more that N4P theoretically could be close enough quality wise to make N3 not worth it to Apple. But it could be worth it to AMD to stick to N3 if it means much more capacity... even if the cost means it has to be super high margin products only like Epyc.

If N3 is way underutilized, wouldn't TSMC temporarily discount to have customers use it anyway for better utilization? AFAIU a lot of the cost for TSMC is the initial investment of setting up the capacity & the process.

 

[jpiniero]

If N3 is way underutilized, wouldn't TSMC temporarily discount to have customers use it anyway for better utilization?

Yeah. Course they could also jack up N4P's prices too.

 

[moinmoin]

I don't think AM5 socket will have the features that a true HEDT would need.

I don't think the TR brand needs true HEDT features, it just needs enough cores to rip threads. 16 cores is already common on AM4, so if TR is to be unified with AM5 as soresu suggested, I'd use that brand for Ryzen chips with >16 cores. But in any case in the grand scheme of things this is a really negligible area.

Pretty sure if it gets that bad, Apple will retreat to N4, and yes that might be a future problem for AMD if TSMC can't pivot quickly enough. But I do not think it will affect Zen4.

I guess it will affect Zen 4, but not by surprise. AMD is adapting nodes to their needs anyway, that's what they take the additional time for, so either they manage to make good use of a bad N3 (and TSMC turns that into a more popular N3 variant) or AMD moves to an N4 variant as well in which case TSMC would accommodate the move of demand and increase N4 throughput by moving EUV machines intended for N3 to N4 instead. It's all in constant flux in any case so unless there's a total breakdown of communication at TSMC it should be business as usual.

 

[Joe NYC]

Intel only confirmed they are using N3, not for what.

Their Client slide quite clearly shows 2 successive client nodes (Meteor Lake and Arrow Lake) both using N3 for GPU:

 

[Saylick]

If N3 is way underutilized, wouldn't TSMC temporarily discount to have customers use it anyway for better utilization? AFAIU a lot of the cost for TSMC is the initial investment of setting up the capacity & the process.

They could, but another issue could be that the number of viable dies that gets produced isn't high enough for the launch volumes needed for the customer. There's only so much you can alleviate with discounts, but schedule is another matter entirely. For Apple to agree to using N3, even if it were discounted such that the price per usable die was the same as if there were no yield problems, it would have to also align with their launch schedule of the product that uses the N3 dies. If it took 3 more months just to build up enough chips for the full launch volume, a delay of 3 months might push out the launch window too far, making N3 a non-starter to begin with.

 

[A///]

The way I see it is Intel has confirmed they'll use N3 for something. There are rumors of issues at TSMC with N3. There is no confirmation. It's also my understanding based on what I've read in the past that Zen 5 was designed for N3, and having to redesign it for N4 would require a considerable amount of work to be redone. The N3 rumors are presumably based on a yields issue. In the case of Apple, would they take a backseat when they can throw money at the problem and regain that spent money through higher prices? It's incorrect for me to say this, but Apple is very much Commander Pipecleaner for any new process at TSMC.

 

[uzzi38]

Intel only confirmed they are using N3, not for what.



I still don't think it's a "Not Ready" issue, more that N4P theoretically could be close enough quality wise to make N3 not worth it to Apple. But it could be worth it to AMD to stick to N3 if it means much more capacity... even if the cost means it has to be super high margin products only like Epyc.

The only Zen 5 product that makes sense on any flavour of N3 at all is Strix Point. And that's because it's late enough that N3E is a potential candidate for the node it's produced on.

I'm gonna be straight with you all - N4/N4P sounds like a far more likely candidate no matter how I cut it for Turin and Granite Ridge. Remember what ExecutableFix said on Zen 5 a while back? It has a max VID of 1.8V as well - there's no way I can imagine first gen N3 being pushed to that level under any circumstances at all.

 

[MadRat]

Why not go with your simplest components on N3, like the stacking cache? Having faster cache or very low heat-producing cache, when cache will dominate your product, sounds like a good fit. Get experience with the process, then migrate CPU architecture over to it.

 

[Ajay]

Pretty sure if it gets that bad, Apple will retreat to N4, and yes that might be a future problem for AMD if TSMC can't pivot quickly enough. But I do not think it will affect Zen4.

Apple will likely scrounge what it can and release the next iPhone with a more limited supply as I expect TSMC is working double overtime to improve yields. Plus, I'm sure the A16 design was too far along for a pivot.
Wafer allocations for 2022 were already set, so I don't see how TSMC could cut back on AMD wafer supply without losing face (or offering up some sweetheart deal to avoid losing face).

Perhaps it was a poor choice to stay with FinFET on the N3 node. Seemed a bit dicey to me, but TSMC seemed very confident. If N2 isn't GAAFET, I would be shocked.

 

[Hans Gruber]

AMD is several nodes behind the cutting/bleeding edge technology from TSMC. That is a good thing. That gives TSMC time to improve their 3nm silicon. I think 5nm TSMC is well over 2 years old right now and Zen 4 isn't even out yet.

 

[Hitman928]

AMD is several nodes behind the cutting/bleeding edge technology from TSMC. That is a good thing. That gives TSMC time to improve their 3nm silicon. I think 5nm TSMC is well over 2 years old right now and Zen 4 isn't even out yet.

Not sure where you are getting several nodes behind from, AMD is currently releasing products that are 1 node behind TSMC's latest and are about to release products on 5 nm which is their most advanced node. TSMC 4 nm does release later this year, but that is more like TSMC 5+nm and would probably be too late for AMD's plans. AMD is also using a customized version of the node which always takes additional time.

 

[uzzi38]

Why not go with your simplest components on N3, like the stacking cache? Having faster cache or very low heat-producing cache, when cache will dominate your product, sounds like a good fit. Get experience with the process, then migrate CPU architecture over to it.

Cache makes the least sense because SRAM scaling past N7 is really quite poor.

 

[jpiniero]

The only Zen 5 product that makes sense on any flavour of N3 at all is Strix Point. And that's because it's late enough that N3E is a potential candidate for the node it's produced on.

I'm gonna be straight with you all - N4/N4P sounds like a far more likely candidate no matter how I cut it for Turin and Granite Ridge. Remember what ExecutableFix said on Zen 5 a while back? It has a max VID of 1.8V as well - there's no way I can imagine first gen N3 being pushed to that level under any circumstances at all.

Having the APUs on a better node seems wrong.

 

[uzzi38]

Having the APUs on a better node seems wrong.

Not saying it is or it isn't, just saying it's the only one that could make sense.

 

[Thibsie]

Not sure where you are getting several nodes behind from, AMD is currently releasing products that are 1 node behind TSMC's latest and are about to release products on 5 nm which is their most advanced node. TSMC 4 nm does release later this year, but that is more like TSMC 5+nm and would probably be too late for AMD's plans. AMD is also using a customized version of the node which always takes additional time.

I guess 4nm is to 5nm what 6nm is to 7nm ?

 

[Thibsie]

Having the APUs on a better node seems wrong.

Deleted.

 

[jpiniero]

I guess 4nm is to 5nm what 6nm is to 7nm ?

4 and friends use the same production lines, right? That's not the case with 6.

 

[DisEnchantment]

The only Zen 5 product that makes sense on any flavour of N3 at all is Strix Point. And that's because it's late enough that N3E is a potential candidate for the node it's produced on.

I'm gonna be straight with you all - N4/N4P sounds like a far more likely candidate no matter how I cut it for Turin and Granite Ridge. Remember what ExecutableFix said on Zen 5 a while back? It has a max VID of 1.8V as well - there's no way I can imagine first gen N3 being pushed to that level under any circumstances at all.

N4X would be the only candidate supporting much higher drive voltages and that too only in the whereabouts of 1.2V. And N3 cuts voltages even more vs N5.
Even N7 would not be able to reliably handle such drive voltages (Not sure OG Zen on 14LPP could also handle such voltages reliably over a period of time)

The only reason I could think of that the processor could request VID of 1.8V is when it has an integrated voltage regulator which would not be unexpected given AMD's numerous patents on this item.
Higher VID means lower I2R losses (if power is same) right up to the VDDM plane with very short distances to the logic (which is the whole point of integrated voltage regulator)
This also allows to cut the number of VDD pins on the socket beside cutting aforementioned I2R losses.

 

[moinmoin]

Apple will (...) release the next iPhone with a more limited supply

Can't see such a launch from Apple happening. If TSMC pushes Apple to such an unavoidable choice I expect Apple to think twice about future cooperation with TSMC.

Whatever happens we should expect TSMC's close customers (as at least Apple, AMD and MediaTek are) to be privy to any potential internal issues as they crop up and work together on possible workarounds and alternate solutions accordingly.