Solved! Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

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What do you expect with Zen 4?


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NostaSeronx

Diamond Member
Sep 18, 2011
3,571
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Sound reasoning, but it doesn't answer at all what's up with the extended WSA between GloFo and AMD. An additional $1.4 billion until 2024 when it was widely thought that the WSA would run out and not be renewed in 2021. Did the WSA turn into a poisonous pill for GloFo instead AMD, securing 14/12nm Fin production for AMD until 2024 while GloFo wanted to convert those fabs earlier?
The WSA via pre-orders only has secured 14nm/12nm Fin production up to 2023. Which is the year where GlobalFoundries will be increasing 45nm&12nm FD production at Malta.

AMD relationship with GloFo is in the know. So, any changes to GloFo's plans would be forwarded ahead of time to AMD. In this scenario, with all info gathered, AMD would transfer EPYC/Ryzen/V&R-series away to TSMC. While reviving Opteron(cost-effective Datacenter), Sempron(cost-effective Personal Computing), G-series(cost-effective Embedded and Other via SCBU). This also includes GlobalFoundries getting the low-end GPU market again.

2022 = Fin production(1st-half+2nd-half), AMD's FDSOI locks in development(2nd-half)
2023 = Fin production goes down to zero(2nd-half), AMD's FDSOI ramps to production(2nd-half)
2024/2025 = Only FDSOI production via AMD at GF going forward.

Began 28nm production at ~$6000 USD(2014) => Enter 22nm production at ~$2000 USD(2024)
With 14nm/12nm Fin being stuck at ~$4000 USD(2022+) for AMD, with the price hike to others pushing it to Samsung's/TSMC's near~$5500 USD levels.

Higher capacity, lower costs for AMD, and lower masks, process steps for GloFo => shorter lead times, and higher profit margins for both with FDX.

TSMC handles premium and higher ASP => better deals and more funding for enhanced FinFETs
GloFo handles cost-sensitive and lower ASP => more stable manufacturing capacity for FDSOI

Lower ASP is given by the lower price point from introduction of 28nm&/14nm at $6000-2014&$8000-2017 USD. Given same area in a mature insert means lower price point for similar performance to 14nm, lower power to 14nm, reduced cost of development(AMD&SCBU) and reduced TTM, etc.

TSMC gained the LP-patent set from GlobalFoundries anyway:
The companies have agreed to a broad life-of-patents cross-license to each other’s worldwide existing semiconductor patents as well as those patents that will be filed during the next ten years as both companies continue to invest significantly in semiconductor research and development.

12LP/7LP/5LP/3LP plans that AMD was aware of is better implemented by TSMC. Money$$$, Multiple Node technicians, multiple fab modules, multi-continent 16nm/12nm/5nm offshore fabs known, etc.
The above specifically: Technology research covering 14nm, 10nm, 7nm, 5nm, 3nm CMOS Finfet technologies for mobile SoC/ASIC. <== Left GF in 2017
GlobalFoundries has yet to implement SSRW High Mobility FinFETs as per 2016-IEEE for 7nm/5nm FinFETs and 2019-IEEE for 14nm/12nm FinFETs. Which AMD might be using if they switch to TSMC, rather than stay at GloFo. In this case, AMD is likely to get a semi-custom customer that wants to add networking accelerators to a Zen++ SoC on TSMC, or whatever. Which Zen++ would be the cheapest option of Zen architectures at TSMC.

A move from GloFo to TSMC is more secure given Zen's market and largely unsuccessful GlobalFoundries SCBU. If they were at TSMC, they wouldn't have failed.
GlobalFoundries FinFET = Ghost Town, one module that was exclusive to FinFETs and is now in transition to FDSOI.
TSMC FinFET = Growing Metropolis, several modules, includes Japan FinFET and Dresden FinFET fabs (and Nanjing FinFET fab), with extension of Arizona FinFET fab.

There is also a better trend of support of custom Zen core implementations at TSMC.

Zen & Dhyana at GlobalFoundries, pretty much in the decay of demand for Zen(preference of TSMC killing Zen-GloFo) and Dhyana is dead.
Zen2, Zen2-Sony, Zen3, Zen4, Zen4c... why not add more on 16nm/12nm.

On the IOD argument, TSMC is more experienced on the I/O FET. So, naturally TSMC's IOD will be superior to GlobalFoundries' IOD.

Basically, everyone is abandoning 14LPP/12LP/12LP+, for TSMC 16FF/12FF or Samsung 14LPP/14LPU/11LPU. However, some customers are simply doing 84CPP-7.5T on 12nm-Fin to go to 84CPP-7.5T on 12nm-FDX; FDXcelerator fast-track. Giving more credence that GlobalFoundries will swiftly down ramp(killing FinFETs) once a replacement node pops up. By the way, 12FDX is definitely doing some form of risk production this year.

Fab8 Device Director 14LPP/12LP/12LP+/12FDX/45RF
Successful technologies deliverables : 45RF | 12FDSOI | 12LP FINFET | Silicon Photonics
Malta 12FDX integration for 1 year 2 months (at edit: Jan 2021-Present)
Malta 12FDX FEOL/MOL process optimization for 2 years 8 months (at edit: August 2019-Present)
Malta/Essex Junction ESD/Latchup development lead for 12LP, 12FDX, 22FDX, and 28SLPe (at edit: June 2021-Present for 12FDX)

Cut extremely short, NPI/NTO(anything new) goes to TSMC if Zen-related; already apparent with RDNAx/CDNAx being TSMC-exclusive as well.

AMD/GlobalFoundries Legacy/Obsolete Big Core/Big CU, etc>> these get moved to TSMC w/ a more aggressive SCBU at TSMC in preparation.
2023+ =>
AMD/GlobalFoundries New/Modern Small Core/Small CU, etc. Separation of node and fab between Little cores(low-cost) and Big cores(premium-cost). Which reflects GlobalFoundries strategy on prioritizing low-cost pervasive semiconductors.
 
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AAbattery

Junior Member
Jan 11, 2019
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After I compared to previous launch timeframes, I would have been more surprised if they released it Q4 or later, it would have meant a delay because of a problem or more time to sell Genoa before launching Raphael.

Zen 1 Q3 2015 tapeout, March 2017 desktop launch
Zen 2 Q1 2018 tapeout, sampling mid 2018, July 2019 desktop launch
Zen 3 early Q2 2019 tapeout, sampling Q4 2019, November 2020 desktop launch
Zen 4 tapeout mid 2020?, In AMD labs before August 3, 2020 according to Bits and Chips on Twitter

I'm excited to see what they did with the IO die and all those extra transistors in the cores, since I was surprised when I found out the ccd is over 72 mm².
 

deasd

Senior member
Dec 31, 2013
456
598
136
It is very fits into 'few weeks after Computex' statement which means July and August, or maybe September first half.
 

DrMrLordX

Lifer
Apr 27, 2000
20,519
9,606
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Zen 4 was never delayed and is not launching early.
Permit me to disagree. Had they prioritized AM5/Raphael over Genoa, they probably could have had it ready by April, and their 15-18 month cadence reflects that. July/August is still not as bad as December (as some had feared/hoped).

It is very fits into 'few weeks after Computex' statement which means July and August, or maybe September first half.
If you look at Greymon's subsequent replies, you will see he seems to think that it will be before September.
 

Joe NYC

Golden Member
Jun 26, 2021
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The WSA via pre-orders only has secured 14nm/12nm Fin production up to 2023. Which is the year where GlobalFoundries will be increasing 45nm&12nm FD production at Malta.

AMD relationship with GloFo is in the know. So, any changes to GloFo's plans would be forwarded ahead of time to AMD. In this scenario, with all info gathered, AMD would transfer EPYC/Ryzen/V&R-series away to TSMC. While reviving Opteron(cost-effective Datacenter), Sempron(cost-effective Personal Computing), G-series(cost-effective Embedded and Other via SCBU). This also includes GlobalFoundries getting the low-end GPU market again.

2022 = Fin production(1st-half+2nd-half), AMD's FDSOI locks in development(2nd-half)
2023 = Fin production goes down to zero(2nd-half), AMD's FDSOI ramps to production(2nd-half)
2024/2025 = Only FDSOI production via AMD at GF going forward.

Began 28nm production at ~$6000 USD(2014) => Enter 22nm production at ~$2000 USD(2024)
With 14nm/12nm Fin being stuck at ~$4000 USD(2022+) for AMD, with the price hike to others pushing it to Samsung's/TSMC's near~$5500 USD levels.

Higher capacity, lower costs for AMD, and lower masks, process steps for GloFo => shorter lead times, and higher profit margins for both with FDX.

TSMC handles premium and higher ASP => better deals and more funding for enhanced FinFETs
GloFo handles cost-sensitive and lower ASP => more stable manufacturing capacity for FDSOI

Lower ASP is given by the lower price point from introduction of 28nm&/14nm at $6000-2014&$8000-2017 USD. Given same area in a mature insert means lower price point for similar performance to 14nm, lower power to 14nm, reduced cost of development(AMD&SCBU) and reduced TTM, etc.

TSMC gained the LP-patent set from GlobalFoundries anyway:
The companies have agreed to a broad life-of-patents cross-license to each other’s worldwide existing semiconductor patents as well as those patents that will be filed during the next ten years as both companies continue to invest significantly in semiconductor research and development.

12LP/7LP/5LP/3LP plans that AMD was aware of is better implemented by TSMC. Money$$$, Multiple Node technicians, multiple fab modules, multi-continent 16nm/12nm/5nm offshore fabs known, etc.
The above specifically: Technology research covering 14nm, 10nm, 7nm, 5nm, 3nm CMOS Finfet technologies for mobile SoC/ASIC. <== Left GF in 2017
GlobalFoundries has yet to implement SSRW High Mobility FinFETs as per 2016-IEEE for 7nm/5nm FinFETs and 2019-IEEE for 14nm/12nm FinFETs. Which AMD might be using if they switch to TSMC, rather than stay at GloFo. In this case, AMD is likely to get a semi-custom customer that wants to add networking accelerators to a Zen++ SoC on TSMC, or whatever. Which Zen++ would be the cheapest option of Zen architectures at TSMC.

A move from GloFo to TSMC is more secure given Zen's market and largely unsuccessful GlobalFoundries SCBU. If they were at TSMC, they wouldn't have failed.
GlobalFoundries FinFET = Ghost Town, one module that was exclusive to FinFETs and is now in transition to FDSOI.
TSMC FinFET = Growing Metropolis, several modules, includes Japan FinFET and Dresden FinFET fabs (and Nanjing FinFET fab), with extension of Arizona FinFET fab.

There is also a better trend of support of custom Zen core implementations at TSMC.

Zen & Dhyana at GlobalFoundries, pretty much in the decay of demand for Zen(preference of TSMC killing Zen-GloFo) and Dhyana is dead.
Zen2, Zen2-Sony, Zen3, Zen4, Zen4c... why not add more on 16nm/12nm.

On the IOD argument, TSMC is more experienced on the I/O FET. So, naturally TSMC's IOD will be superior to GlobalFoundries' IOD.

Basically, everyone is abandoning 14LPP/12LP/12LP+, for TSMC 16FF/12FF or Samsung 14LPP/14LPU/11LPU. However, some customers are simply doing 84CPP-7.5T on 12nm-Fin to go to 84CPP-7.5T on 12nm-FDX; FDXcelerator fast-track. Giving more credence that GlobalFoundries will swiftly down ramp(killing FinFETs) once a replacement node pops up. By the way, 12FDX is definitely doing some form of risk production this year.

Fab8 Device Director 14LPP/12LP/12LP+/12FDX/45RF
Successful technologies deliverables : 45RF | 12FDSOI | 12LP FINFET | Silicon Photonics
Malta 12FDX integration for 1 year 2 months (at edit: Jan 2021-Present)
Malta 12FDX FEOL/MOL process optimization for 2 years 8 months (at edit: August 2019-Present)
Malta/Essex Junction ESD/Latchup development lead for 12LP, 12FDX, 22FDX, and 28SLPe (at edit: June 2021-Present for 12FDX)

Cut extremely short, NPI/NTO(anything new) goes to TSMC if Zen-related; already apparent with RDNAx/CDNAx being TSMC-exclusive as well.

AMD/GlobalFoundries Legacy/Obsolete Big Core/Big CU, etc>> these get moved to TSMC w/ a more aggressive SCBU at TSMC in preparation.
2023+ =>
AMD/GlobalFoundries New/Modern Small Core/Small CU, etc. Separation of node and fab between Little cores(low-cost) and Big cores(premium-cost). Which reflects GlobalFoundries strategy on prioritizing low-cost pervasive semiconductors.
BTW, would you know which of to Global Foundries fabs makes the Tesla infotainment system?
 

NostaSeronx

Diamond Member
Sep 18, 2011
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BTW, would you know which of to Global Foundries fabs makes the Tesla infotainment system?
Fab 8, Module 1, is the fab that is producing the Picasso-H chip for Tesla currently. It is the only module at GloFo that does FinFETs, these GF fabs don't do FinFETs;
Fab 1 Module 1
Fab 1 Module 2
Fab 1 Module 3 <- not complete till ~2024.
Fab 7 Module 1(7)
Fab 7 Module 2(7G)
Fab 7 Module 3(7H) <- not complete till ~2023.
The above which are anywhere between 55-nm to 22-nm, currently.

TSMC's Fab 15/Fab 18, etc have three(A-Fab)+three(B-Fab) modules that output 1.67x more per module than Fab 8, Module 1.
~30,000 wafers/month GF -> ~300,000 wafers/month TSMC.

Singapore is at net income target, Dresden is close to net income target, Malta since FinFET-focus has always been net income loss.

On every front Intel expects to kill GlobalFoundries in America:
Every potential market GlobalFoundries could enter with 14LPP/12LP/12LP+ is better served by 14GP, etc. Better AI/Automotive/Datacenter/Crypto/etc experience, it also helps that a few GloFo Fin-management went to Intel for Design Enablement management.
AMD isn't going to Intel, #2 is going to 12FDX, #3/#4/#5 on 12LP is likely to go to 14GP which is a straight-forward port: 78CPP/48FP/64Mx -> 70CPP/42FP/52Mx(14GP(+)) or straight side-ways port: 84CPP/48FP/64Mx -> 84CPP/42FP/52Mx(14GP++)
 
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Joe NYC

Golden Member
Jun 26, 2021
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Fab 8, Module 1, is the fab that is producing the Picasso-H chip for Tesla currently. It is the only module at GloFo that does FinFETs, these fabs don't do FinFETs;
Fab 1 Module 1
Fab 1 Module 2
Fab 1 Module 3 <- not complete till ~2024.
Fab 7 Module 1(7)
Fab 7 Module 2(7G)
Fab 7 Module 3(7H) <- not complete till ~2023.
The above which are anywhere between 55-nm to 22-nm, currently.

TSMC's Fab 15/Fab 18, etc have three modules that output 1.67x more per module than Fab 8, Module 1.

Singapore is at net income target, Dresden is close to net income target, Malta since FinFET-focus has always been net income loss.
Ok, so that's the Malta, New York fab then. I think another potential Automotive client (as has been rumored) might be very pleased about that location, since the Automotive customers have been supporting various efforts to diversify from high concentration of supply coming from South East Asia.
 

biostud

Lifer
Feb 27, 2003
17,134
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I am planning to build a zen4 machine, but I also plan to bu all my parts at the same time so I'll hold on until I can get:
a nvme PCIe 5.0 drive
DDR5 at a reasonable price
next generation video card at "reasonable" price (whatever and whenever I might think that is)
 

Kedas

Senior member
Dec 6, 2018
355
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DDR5 prices are going in the right direction so it may not be a big issue releasing AM5 in Q3.
Although intel has a good low thread load score with 'low prices'.... like 12700k.
Not sure if multi-thread 8 Core Zen4 will beat the 12700K for only $400 (probably less by then.)

Maybe they launch earlier because they expect not having much margin with intel in Q1 2023 hence waiting will hurt sales and market share. Also the current numbers are clearly showing a rise in intel sales and a drop in AMD sales (not very big), add another 6 months to that and it doesn't look that good any more.

edit:
DDR5 32GB kit CMK32GX5M2A4800C40 dropped from 479Euro to 299Euro (incl. 21% tax) in 1 month. (since there is enough stock now)
Performance is about equal to DDR4-4000 C16, cost 270 Euro. F4-4000C16D-32GVK
 
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DisEnchantment

Golden Member
Mar 3, 2017
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This is Genoa: The clue is here above the "Bits" column where it says _ccd[11:0] for the 12 CCD's of Genoa.
This manual has all the AVX512 stuff as well. You were probably looking for a similar 512-bit "full width" flag :)
It is still 'reserved' here in this version. Can go either way...
Well, since they updated the manual already to indicate _ccd[11:0], I suppose this is going to be the way it is and I hope it to be that way too.
In Zen 3, the core proper w/o L2 is around twice the size of the FPU. Straight up doubling the FPU will make it same size as the core which is very lopsided for an opportunistic workload.
So I would suppose, the FPU is increased by 40-50% at best, similar to how Intel did when supporting AVX512 on their client CPUs.
This gives it lots of room to allocate more MTr to the core proper based on leaked Zen4 CCD sizes.

What is still intriguing to me though is AMD's claimed 2x density improvement for optimized N5, not sure how they calculated that.
From Zen 2 launch, Papermaster's stated 2x density (vs 14LPP) came to mean
Zeppelin --> Matisse roughly ~26MTr/mm2 --> 52MTr/mm2 (CCX to CCX comparison not possible though, numbers not available)
Raven Ridge --> Renoir roughly 31MTr/mm2 --> 62MTr/mm2

Is AMD's stated 2x density bump for optimized N5 (vs optimized N7) meaning
Vermeer --> Raphael 52 MTr/mm2 --> 104 MTr/mm2
If this is the case, Raphael will have an incredible amount of MTr per core+L2, reaching Apple's or Intel's level (which they have not been disclosing lately)

Even if only 2x for the logic, the core will still get a hefty >1.6x bump in MTr.
And strictly going by TSMC's values would still make the core a very very hefty upgrade, >2x MTr for L2, >1.5x MTr for FPU, >1.4x MTr for Core (also considering minor increase in MTr for all other blocks)
Either way, the topic is intriguing, it give the ranges of the Core+L2 MTr bump for a range of at worst 1.5x to 2.2x if the same metric of Zen --> Zen2 density scaling used by AMD.
 

DisEnchantment

Golden Member
Mar 3, 2017
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I was also surprised to hear that AMD previously licensed Xilinx technology and has been integrating that IP into its processor roadmap with the first expected products in 2023. Surprise!
Zen 5 ?? o_O


 

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