a bit of crazy/fun speculation from me. Recent leaks point to Ryzen using a Fan-out package, so it's possible Epyc is using it too. Looking at the leak from Gygabyte, I'm estimating the size of such fan-out area has to be around 31x65mm big. Looking online at what different companies offer, found an ASE fan-out packging page, in which they state that with "FOCoS", which is aimed at servers and networking, it's possible to make a package with a length of 67mm, barely enough for potential Epyc package. And on a standard wafer, about 20 such packages can be made. Edit: TSMC offers InFO_OS, which seems similar, and is qualified for 65x65mm packages in 2019.
View attachment 55674
Nice job with this.
There seems to be a quite a bit of empty space on 2 sides of this arrangement. It makes me wonder if AMD might be adding some additional silicon there. Could this support possibly putting some HBM memory in the package? Or some sort of FPGA or customized chips for things like encoding / decoding / networking...
If there is nothing else, just 12 chiplets connected to IO Die, is this the most optimized approach, given that there will be:
- additional cost to cost to the fan out package and assembly costs
- AMD still has the SerDes connection with its limitations
- bandwidth increase will only be linear,
- power savings may be limited.
- may limit the desktop / AM5 to higher market segments, no entry level CPUs
It seems that EMIB / EFB could be:
- cheaper
- no more SerDes, latency hit
- lower power use
- greater bandwidth potential
I wonder if this will end up an interim solution for a single generation.
Or, there may be more to this solution that we don't know yet. Something beyond just IOD-CCD links
One idea: Cutress had an article / video speculating that AMD could use interposer, which could provide a mesh interconnect between cores of the package, replacing the ring bus
Alternatively, quadrants could be NUMA, groups, and there could be a faster chiplet to chiplet interconnect within a quadrant constituting NUMA group.
Another AMD exec was hypothesizing about a mesh chiplet to chiplet interconnect, possibly providing very fast access to each other's L3 caches. But that could be quite messy, and if all the links would need a SerDes, also power hungry.
Alternatively, it could be only quadrant to quadrant mesh of SerDes based connections, as opposed to chiplet to chiplet...