Solved! Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[DisEnchantment]

Hopefully this means direct compute chiplet communication? Though, it could just as well only be for IO-compute chiplet connections, bah.

In magical Christmas land where everything my layman mind can dream comes true, we'd get direct die-to-die CCDs, and they'd use each other's massive stacked L3 as an L4 too. Like the Zen 3 CCX unification all over again almost.

EDIT: in hindsight I'm not sure why I was thinking any of this would lead to direct CCD-CCD communication.

It is not about CCD-CCD communication but it is more generic. Additionally the IF/GMI SerDes are there all the same, just that they are routed differently and more efficiently.
GMI3 supposedly can hit really high BW (up to 64 Gbps, far higher than GMI2 from Zen3/2 at 25 Gbps) which means more Rx/Tx lines which would have been difficult going through substrate, but much easier through RDL within the fanout because of far higher interconnect density. Assuming the FO is deployed of course.

In any case L3 of the other CCDs are accessible just the same like in Zen 3 2x CCD parts.

 

[eek2121]

All of the presentations were pretty boring, but what else is there to expect when no one has any of their next generation products launching until the end of the year?

Spring = end of the year?? Q3 = end of the year??

EDIT: dare I say, AMD has NO confirmed product
launches EOY currently?

 

[DisEnchantment]

With Zen4 launching in H2, it seems uncertain to have STP to be ready for laptops in 2024 spring refresh.
PHX for sure won't have such a problem, it will just be right on time.
But Strix Point seems doubtful, having a Zen5 and a Zen4D arrangement would mean Zen 5 launches within 12 months of Zen 4.
While Greymon is saying this, I am not sure it is still valid now


I wonder if there is a gap filler between PHX and STP.
None of the usual suspects (Patrick Schur, Greymon, Execufix) talked about anything in between.

Also with STP supposedly being fully chiplet based, I wonder if they will use SerDes at all, just direct die on die stacking with something like SoIC.
GMI will not cut it, the efficiency loss is just too much.

 

[Mopetar]

Spring = end of the year?? Q3 = end of the year??

EDIT: dare I say, AMD has NO confirmed product
launches EOY currently?

Next generation. Zen 3D is still Zen 3 and on the AM4 platform. Any Radeons are 6000 series, not RDNA 3 which we haven't really heard anything about. Same with NVidia where the cards they announced are 3000 series Ampere cards. Outside of the 3090 Ti the cards are all low-end as well, so not as exciting for most here.

Neither AMD or Intel are going to have the next generation CPUs out in the first half of 2022. Anything new isn't coming out until Q3 at the earliest. End of the year is a catch-all blanket statement to indicate that anything we do get will be closer to the end of 2022 than it will be to the start of it. We might get some stuff as early as July, but if you average it all together, new next generation CPUs/GPUs are going to be towards the end of the year.

 

[Ajay]

It is not about CCD-CCD communication but it is more generic. Additionally the IF/GMI SerDes are there all the same, just that they are routed differently and more efficiently.
GMI3 supposedly can hit really high BW (up to 64 Gbps, far higher than GMI2 from Zen3/2 at 25 Gbps) which means more Rx/Tx lines which would have been difficult going through substrate, but much easier through RDL within the fanout because of far higher interconnect density. Assuming the FO is deployed of course.

In any case L3 of the other CCDs are accessible just the same like in Zen 3 2x CCD parts.

And, I would guess, lower power/bit/clock. But I'm not sure, haven't found anything detailed enough on InFO-LSI.

 

[andermans]

View attachment 55570

With Zen4 launching in H2, it seems uncertain to have STP to be ready for laptops in 2024 spring refresh.
PHX for sure won't have such a problem, it will just be right on time.
But Strix Point seems doubtful, having a Zen5 and a Zen4D arrangement would mean Zen 5 launches within 12 months of Zen 4.
While Greymon is saying this, I am not sure it is still valid now
View attachment 55571

I wonder if there is a gap filler between PHX and STP.
None of the usual suspects (Patrick Schur, Greymon, Execufix) talked about anything in between.

Also with STP supposedly being fully chiplet based, I wonder if they will use SerDes at all, just direct die on die stacking with something like SoIC.
GMI will not cut it, the efficiency loss is just too much.

Note that Greymon seems to be someone who has significant inside info, which is much better than just assuming 18 months between products. I believe Zen4 isn't delayed at this point, which would likely mean that whatever roadmap he would have had access to is likely still accurate.

(As an aside, I'd expect work in Zen4 and Zen5 to happen somewhat in parallel, as making a new core takes more than 18 months of wall time. This means that delay in one core don't necessarily apply to the other.)

 

[turtile]

Note that Greymon seems to be someone who has significant inside info, which is much better than just assuming 18 months between products. I believe Zen4 isn't delayed at this point, which would likely mean that whatever roadmap he would have had access to is likely still accurate.

(As an aside, I'd expect work in Zen4 and Zen5 to happen somewhat in parallel, as making a new core takes more than 18 months of wall time. This means that delay in one core don't necessarily apply to the other.)

Mike Clark pretty much said that Zen 5 is already design complete (at least that's what it sounded like to me). So I don't think we should be surprised to see Zen 5 come right after Zen 4.

It seems that AMD works on packaging -> core -> packaging -> core. Packaging seems to take more time.

 

[DisEnchantment]

And, I would guess, lower power/bit/clock. But I'm not sure, haven't found anything detailed enough on InFO-LSI.

I don't think InFO, that is WLP, they won't probably do that. Also not EFB confirmed by same person on Reddit.
A cheaper, simpler and chip last fan out is most likely and also which they have been patenting a lot. This way they can assemble it at Tongfu for example instead of TSMC.

Spoiler: PATENTS

10867978 : Integrated circuit module with integrated discrete devices
11011495 : Multiple-die integrated circuit with integrated voltage regulator
10903168 : Multi-RDL structure packages and methods of fabricating the same
11211332 : Molded die last chip combination
11011466 : Integrated circuit package with integrated voltage regulator


20210313269 : INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED VOLTAGE REGULATOR
20210057352 : FAN-OUT PACKAGE WITH REINFORCING RIVETS

Greymon has been saying they build up new facilities for something in China Mainland too.

SoIC (and all Front end packaging) is done at TSMC, TSMC is not very interested in backend services (e.g. CoWoS, InFO etc) on their own beside developing the tech and they have outsourced a bunch of it to ASE actually.

Note that Greymon seems to be someone who has significant inside info, which is much better than just assuming 18 months between products. I believe Zen4 isn't delayed at this point, which would likely mean that whatever roadmap he would have had access to is likely still accurate.

Yeah, I know Greymon has been quite on the mark, (maybe just behind Execufix and Patrick)
But I am wondering nonetheless of a potential gapfiller which might indicate something else.

 

[soresu]

(As an aside, I'd expect work in Zen4 and Zen5 to happen somewhat in parallel, as making a new core takes more than 18 months of wall time. This means that delay in one core don't necessarily apply to the other.)

100% certain that AMD has leapfrogging design teams for Zen.

This much has been said at least once by Papermaster is I recall.

Also I don't think that Zen4 is actually delayed in terms of product readiness - AMD simply hasn't been able to put out as much Zen3 product as they would like due to the various supply issues, therefore they cannot capitalise on the R&D costs as well as they would like before transitioning to the next core.

From a business point of view this is not healthy even if you are Intel - and if you aren't it's extremely unhealthy long term.

It wouldn't surprise me if the supply problems are the real reason that Zen3D exists at all on the desktop, to get that extra inch as it were.

 

[eek2121]

With Zen4 launching in H2, it seems uncertain to have STP to be ready for laptops in 2024 spring refresh.
PHX for sure won't have such a problem, it will just be right on time.
But Strix Point seems doubtful, having a Zen5 and a Zen4D arrangement would mean Zen 5 launches within 12 months of Zen 4.
While Greymon is saying this, I am not sure it is still valid now


I wonder if there is a gap filler between PHX and STP.
None of the usual suspects (Patrick Schur, Greymon, Execufix) talked about anything in between.

Also with STP supposedly being fully chiplet based, I wonder if they will use SerDes at all, just direct die on die stacking with something like SoIC.
GMI will not cut it, the efficiency loss is just too much.

It is very possible AMD will release Zen 5 on a much quicker cadence. They know Intel is being pretty aggressive, so if they stand to gain a competitive advantage, they likely will.

Next generation. Zen 3D is still Zen 3 and on the AM4 platform. Any Radeons are 6000 series, not RDNA 3 which we haven't really heard anything about. Same with NVidia where the cards they announced are 3000 series Ampere cards. Outside of the 3090 Ti the cards are all low-end as well, so not as exciting for most here.

Neither AMD or Intel are going to have the next generation CPUs out in the first half of 2022. Anything new isn't coming out until Q3 at the earliest. End of the year is a catch-all blanket statement to indicate that anything we do get will be closer to the end of 2022 than it will be to the start of it. We might get some stuff as early as July, but if you average it all together, new next generation CPUs/GPUs are going to be towards the end of the year.

Once again: AMD has confirmed no EOY launches. None of the rumors even point to an EOY launch of any product. Zen 4 will likely be Q3. RDNA3 will be anywhere from Q3 of this year (probably announced in October) through Q1 of next year. It is very possible AMD will launch nothing in December.

 

[Mopetar]

Once again: AMD has confirmed no EOY launches. None of the rumors even point to an EOY launch of any product. Zen 4 will likely be Q3. RDNA3 will be anywhere from Q3 of this year (probably announced in October) through Q1 of next year. It is very possible AMD will launch nothing in December.

Go back and read what I said and quit being pedantic. I said it was a catch-all term to mean that none of the tech companies would have anything out until much closer to the end of 2022 than the beginning.

 

[biostud]

So where are we on the latest rumors/guesses on zen4? homogenous chiplets or heterogenous? or do we first see heterogenous with zen5? number of cores/chiplet?

 

[SteinFG]

So where are we on the latest rumors/guesses on zen4? homogenous chiplets or heterogenous? or do we first see heterogenous with zen5? number of cores/chiplet?

homogenous, 8 Zen4 cores per chiplet, ryzen 16 cores, epyc 96 cores

Zen 4c is a special CCD with unknown number of cores/chiplet

heterogenous cores are coming with Strix Point in 2024

 

[Abwx]

So where are we on the latest rumors/guesses on zen4? homogenous chiplets or heterogenous? or do we first see heterogenous with zen5? number of cores/chiplet?

That s WCCFTech, but still...

Alleged AMD Ryzen 7000 'Zen 4' 16 Core & 8 Core Desktop CPUs Spotted

AMD's next-generation Ryzen 7000 'Zen 4' 16 & 8 core desktop CPUs have allegedly been spotted over at the MilkyWay@Home database.

wccftech.com

 

[Ajay]

That s WCCFTech, but still...

Alleged AMD Ryzen 7000 'Zen 4' 16 Core & 8 Core Desktop CPUs Spotted

AMD's next-generation Ryzen 7000 'Zen 4' 16 & 8 core desktop CPUs have allegedly been spotted over at the MilkyWay@Home database.

wccftech.com

Given what AMD has said officially, I'd fall over if there are 'efficiency' cores in Zen4.

 

[nicalandia]

How is that a Prototype is running at 5 Ghz on ALL Core while Gaming?

 

[tomatosummit]

Given what AMD has said officially, I'd fall over if there are 'efficiency' cores in Zen4.

Even though there's a lot of nonsense in that article I don't think the 16core chiplet is impossible.
It's read to me more as zen4c bergamo than anything that will go into a ryzen product.
And it doesn't look like 'efficiency' cores specifically either. Just a full fat zen core sharing l2 and unable to run at high frequency due to the stacked l3 thermal insulation. Basically the periphery cores can boost and use the full l2 or all cores are in use at closer to base clocks.
The 35w mention seems very telling as 8x35 is 280 and adding an IO puts it in the ballpark for next generation server cpu power draw.

 

[TBytemaster]

Looks like somebody at WCCF forgot about hyperthreading lol. They've changed their headline to "16 Core & 8 Core".

(Milkyway@home reports threads as "number of processors")

 

[DrMrLordX]

How is that a Prototype is running at 5 Ghz on ALL Core while Gaming?

Probably because the "prototype" is QS-quality silicon with maybe some AGESA bugs in the platform. I would assume, by this point, that the silicon itself would be very close to A0-stepping.

 

[deasd]

That s WCCFTech, but still...

Alleged AMD Ryzen 7000 'Zen 4' 16 Core & 8 Core Desktop CPUs Spotted

AMD's next-generation Ryzen 7000 'Zen 4' 16 & 8 core desktop CPUs have allegedly been spotted over at the MilkyWay@Home database.

wccftech.com

5x integer performance against 5950X?? Looks like some instruction set like avx512 kicked in... floating point perf looks more logical though....

 

[DisEnchantment]

5x integer performance against 5950X?? Looks like some instruction set like avx512 kicked in... floating perf looks more logical though....

That is incorrect. That is why it is important to avoid WCCFTech. They don't care what data they put out, in fact they will intentionally put in controversial data.

Below is a more like for like comparison using Ubuntu native and not virtualized. But still this not really a good indication because the app itself is not for benchmarking.
I removed the GPU benchmark, 5950X on left and new 8 Core ES on right






We have to ask our forum residents doing BOINC/F@H how to interpret these , I have no idea.

Interesting thing here is that the iGPU is not seen, which means this part does not have the iGPU.
It looks like this if there is an iGPU

Either that, or the iGPU does not have a driver yet.

Update:
It seems both the leaked part numbers have already been added to the product master list since 2021 (used for export control by the US Department of Commerce)

https://www.amd.com/system/files/documents/product-master.pdf

 

[eek2121]

L2 cache appears to be doubled.

EDIT: while the application may not be a benchmark, that would appear to indicate a 19% integer uplift. Floating point seems little changed.

 

[naukkis]

L2 cache appears to be doubled.

EDIT: while the application may not be a benchmark, that would appear to indicate a 19% integer uplift. Floating point seems little changed.

Those uplifts are coming from 16 thread system against 32 threads....... Pretty hefty uplift.

 

[inf64]

L2 cache appears to be doubled.

EDIT: while the application may not be a benchmark, that would appear to indicate a 19% integer uplift. Floating point seems little changed.

How can you calculate the IPC improvement without knowing the clock speeds of the ES in particular workloads? Also, the ES is 8core versus 16C Zen3.

 

[Tuna-Fish]

How can you calculate the IPC improvement without knowing the clock speeds of the ES in particular workloads? Also, the ES is 8core versus 16C Zen3.

uplift ≠ ipc.

But yeah, if that is speed across all cores, that's a 2.5x improvement. As I understand it, some (but not all) boinc workloads support AVX-512. If milkyway@home is among them, it would make a lot of sense if that's what's happening here.