Solved! Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[uzzi38]

I can't wait to see how this will affect battery life among other thinds (is Rembrant 6nm as well?) .

Certainly a much needed change, considering Cezanne was essentially Renoir with the CCX replaced and L3 doubled. There hasn't been much change to the uncore for 2 years.

Yes it is N6 and yes battery life is the thing I can't wait to see as well.

 

[Joe NYC]

I don't see how it makes a lot of sense to have 2 chipsets. How many people are really running out of USB / SATA ports?
(for desktop Ryzen Zen 4)

I would think that the bottleneck is more on the NVMe side, lanes directly from the CPU, where I could see the need for more than 1x4 lanes.

Maybe there are some modularity advantages I am not seeing right away...

https://twitter.com/i/web/status/1473228052666925060

 

[xilli_fiberbit]

Why X670=2xB650 ? B650 doesn't even exist

X670 could be a IOD in 6nm, like X570 is the IOD 12nm

 

[Joe NYC]

Why X670=2xB650 ? B650 doesn't even exist

X670 could be a IOD in 6nm, like X570 is the IOD 12nm

B650 is probably going to be the replacement of B550.

 

[Thibsie]

B650 is probably going to be the replacement of B550.

Really ?

 

[moinmoin]

Curious about what those are.

Aside all the efficiency improvements one should expect since Renoir the uncore also serves as the test platform for AM5.

 

[xilli_fiberbit]

They said too on the chinese page:

Solve the puzzle: x670 starts to use 12Vonly

It is very difficult to make itx .Could it be that the x670 chip heats up too much, much larger than the x570

So comeback of the fan on the chipset ?

 

[Tuna-Fish]

How many people are really running out of USB / SATA ports?
(for desktop Ryzen Zen 4)

I would think that the bottleneck is more on the NVMe side, lanes directly from the CPU, where I could see the need for more than 1x4 lanes.

I absolutely agree that with the rise of cheap NVMe storage, the most limited IO type on desktop are the pci x4/NVMe ports. I don't think the system needs to provide for all of those ports to work at the same time (people use extra slots for extra capacity, not for running superfast raid configs), and the extra latency for using a hub between the device and the CPU is negligible for storage uses. I suspect that AMD thinks so too, and that the B650 (if it's called that) has more PCIe lanes. Let's say, 3x4, with one of them splittable into individual pci/sata like the two lanes in B550, so a normal midrange B550 might have:

-1 PCIe x16 from the CPU
-1 NVMe x4 from the CPU
-2 NVMe x4 from the chipset
-2 PCIe x1 from the chipset
-2 sata 6GBps from the chipset.

Then a doubled up config would take the x4 from the CPU, but provide up to 3 extra x4 from the chipset.

 

[eek2121]

Curious about what those are.

AMD has confirmed significantly better power management, for starters.

 

[Thibsie]

AMD has confirmed significantly better power management, for starters.

Excellent news. Hope they'll be available on the market sooner than Cezane/Lucienne.
Some laptops never came to market.

 

[xilli_fiberbit]

X670 chipset is for AM5 platform and will introduce too the 12VO, the more heat generated by this chip can be explained because it's a MCM chip with two B650. It can explain why on chinese forum they talks about a X670 which is doubled compared to B650

 

[leoneazzurro]

In the meanwhile some leaker yesterday on Twitter said that Raphael will be launched at Computex, so earlier than some expected. To be taken with a big grain of salt, of course.

 

[xilli_fiberbit]

But Rembrandt AM5 only in Q3 2022

Zen 4 in Computex, and seems only suport D5 (cpu can both), what mean "only suport D5" ?

https://twitter.com/i/web/status/1473458150254645249

 

[leoneazzurro]

AMD to reveal some details on Zen4 architecture at CES 2022 - VideoCardz.com

AMD to briefly talk about Zen4 at CES 2022 In an exclusive interview with Antony Leather (Forbes/CrazyTechLab), AMD CTO Mark Papermaster confirmed that Zen4 architecture will be part of the CES 2022 press conference, however, the primary focus will be on updated Zen3 architecture with 3D...

videocardz.com

If AMD starts to share details of Zen4 at CES, the Computex release may be not be far from reality. Or simply, as Genoa samples should be already in selected custormers' hands, they feel there is no point to keep it so tight anymore.

 

[moinmoin]

what mean "only suport D5" ?

DDR5 would be my guess, with "both" referring to DDR5 and DDR4 as per the quoted tweet (likely also LPDDR5 as Van Gogh already supports that).

The nuclear display in Raphael sounds really promising for that matter.

 

[DisEnchantment]

See translation from @kokhua, better than Machine translation

https://twitter.com/i/web/status/1473489665122394112

AMD to reveal some details on Zen4 architecture at CES 2022 - VideoCardz.com

AMD to briefly talk about Zen4 at CES 2022 In an exclusive interview with Antony Leather (Forbes/CrazyTechLab), AMD CTO Mark Papermaster confirmed that Zen4 architecture will be part of the CES 2022 press conference, however, the primary focus will be on updated Zen3 architecture with 3D...

videocardz.com

If AMD starts to share details of Zen4 at CES, the Computex release may be not be far from reality. Or simply, as Genoa samples should be already in selected custormers' hands, they feel there is no point to keep it so tight anymore.

Interview is quite hilarious, Papermaster dodging questions with non statements and before you know it the interview is over and he has given out absolutely zero information.
But 18 months should be the expected time frame, right around Computex or thereabouts

 

[xilli_fiberbit]

The X670 is probably the cIOD used in Raphael but in 6nm will be expensive, AMD can just keep the cIOD which has defect on igfx to make with it the X670

The B650 is a Promotory V2

 

[moinmoin]

See translation from @kokhua, better than Machine translation

Aww man, I was waiting for more opportunities to joke some more about the previous bad translation.

"You need to boldly imagine it! The more outrageous the wave the better!"

 

[deasd]

See translation from @kokhua, better than Machine translation

View attachment 54779

Some points were based on the author's speculation. So that these are not even a leak though.

 

[DrMrLordX]

Computex 2022 release for Raphael would be a nice surprise after all the speculation that it would be Q4. Nice of them to at least adhere to an 18 month cadence. We may see Raphael and Vermeer-X/Zen3d overlap after all!

 

[Joe NYC]

The X670 is probably the cIOD used in Raphael but in 6nm will be expensive, AMD can just keep the cIOD which has defect on igfx to make with it the X670

The B650 is a Promotory V2

That would seem like an overkill and a waste of 6nm capacity.

 

[jamescox]

That would seem like an overkill and a waste of 6nm capacity.

This makes me more suspicious that there will not be any SP5 based Threadripper. Perhaps they will have AM5 go up to 3 cpu chiplets with an HEDT platform using 2 IO die to provide a lot more IO than the regular AM5. Perhaps I am misunderstanding though. An IO die will presumably have 32 pci-express gen 4,at least, possibly gen 5 capable. They could do something like an x8 from the cpu for each chip and provide 24 lanes out from each chip (some used for sata, usb, etc). That would allow close to Threadripper level IO (16 still left from cpu and 48 from chipset = 64 lanes). If they allowed pci-express gen 5 between the chiplets, that could provide more than current Threadripper level IO. Also, the trace lengths have been decreasing with each pci-express generation. Perhaps they daisy chain two IO die to significantly reduce trace lengths. That could actually reduce board cost and complexity. Perhaps an x8 pci-express 5 off cpu to chipset IO die, another x16 for IO, with the remaining x8 going to a second IO die. That could keep trace lengths very short. It wouldn’t make sense for a mini-itx board in that case.

 

[Mopetar]

The market position where Intel has no answer to Threadripper is why there isn't anything new in the pipeline. Just like Intel could get away with sitting on 4 core CPUs for all of those years, AMD can get away with continuing to sell existing TR parts.

They'll probably eventually have something new, but right now they're going to prioritize the areas where they can't rest of their laurels due to competition from Intel or they can make more money. Threadripper is in the awkward middle position where it's not quite as profitable as the server market and not nearly as contested as the desktop and mobile markets.

We'll get some new parts eventually, but there just isn't any pressure on AMD to do it as soon as some might like. Maybe there are some technical hurdles in there as well, but they're not vastly different from what would need to be solved for new server parts.

 

[LightningZ71]

We have to remember, the current Threadripper lineup is quite different from it's origin as well. The WX high end parts are essentially Epyc parts that were repurposed into high end workstation parts either by choice, or because they didn't hit certain efficiency targets in binning. The WX line is a trivial offshoot of the server parts. The lower end Threadripper parts are different enough to require a bit more cost. They continue only because AMD is contractually obligated to continue to support the Zen2 server parts with CCDs. Since they must continue in production, those TR parts help with volume levels. They'll probably disappear when there is no longer a need to make Zen2 CCDs. Will there be a Zen3 low end TR part? Maybe if the chip shortage ever lets up. But, there's really no market need for it at present.

 

[DisEnchantment]

Many thanks to @Hans de Vries for this doc which I picked up from Twitter


One interesting take away from this diagram I was able to dig is DC-SCM, as you can judge from the standard, it is mostly written by Microsoft and Google.
Confidential computing at MS and Google using EPYC Milan is still in beta because of multiple reasons. But I can surmise these below reading some of the bulletins

• MS, Google, TenCent, Oracle and few others identified some weaknesses in the whole chain of SEV.
• There were vulnerabilities in some of the register access when using SEV SNP
• Shortcomings in how the BIOS/EEPROM is accessed and the Versioned Chip Endorsement Key (VCEK) used for SEV is managed
• Securing only the SW and CPU is not enough, you need to secure the whole HW platform.

Seems DC-SCM plans to secure the way BIOS and external EEPROM/Flash/Physical access is managed using an OCP module

Spoiler: DC-SCM Module Architecture

Spoiler: SPI/EEPROM Access

AMD addressed major CVEs in SEV already with firmware update.
And the server ecosystem is also moving to secure the BMC/EEPROM/BIOS/etc as well.
Even JTAG access needs secure unlock, which should have been done long ago, but I guess if the VM is not even encrypted, no need to bother with JTAG access when you can access the process memory directly.

All in all a very impactful change that can be partly (or even majorly) attributed to the introduction of SEV and the CCP.
Doing the rounds right now is a lot of work from AMD and other partners like Google, Microsoft, Tencent and Oracle to bring in SEV-SNP upstream. (Downstream should already be available already)
In fact, hyper-v will have a new VM isolation mechanism written around SEV SNP
Seems Zen 4 will introduce some newer SEV features which Lisa showed in the main slide. (I read from LinkedIn there is a feature called VMG but not very clear what it does)