Something to put in the equation is that I/O die will likely change process, thus going to N7/N6. While the new I/O die will support quite probably PCI-E 5 and DDR5 is a given, the new process should allow anyway substantial power savings, that is, more power can go to to the CCDs at the same power envelope.The opportunity was there and they took it. They could add more transistors in Zen2 without increasing power drastically.
Zen --> Zen2
2x CCX for 8Cores + 2x 8MBL3 @2800 MTr (Entire Zeppelin is 4800 MTr) --> 1CCD/CCX for 8Core + 1x 32MBL3 3800MTr
That's 1.35x MTr gain for 15% IPC and total TDP 95W-->105W
More than half of the 1.35x gain over 2x CCX of Zen1 is due to doubling of L3, addition of 256 bit FP units and addition of GMI and SMU in Zen2 CCD
Real Core+L2 is only ~15% more MTr
Zen2 --> Zen3
~1.1x MTr gain for 19% IPC and total TDP 105W-->105W
Between 25 to 40% MTr gain, IPC?
L3/SMU largely simlar MTr count
About the cores, we don't know how much of the transistor budget went to AVX512, but it is safe to think that doubling the L2 and increasing the IF links frequency (and having 2 IF links per CCD) alone will easily bring a good increase in IPC. Add to this a possible clock frequency increase die to the new process.