Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[DrMrLordX]

My first question would be if the Zen4 design has been completed by now

Genoa's shipping already, so. Unless you think Raphael is going to be radically different . . . you have your answer.

(and yes I know it's "just to hyperscalars" but come on, AMD sat on Milan forever and a day, don't think this is abnormal)

 

[scineram]

Shipping to AMD. For bring up.

 

[eek2121]

It's been only 6 months since Zen 3 launched. The horrible availability makes it feel longer. Milan has launched very recently. There are no signs of any Zen 3 TR to be launched soon. Desktop non-XT models are also still lacking. So the Zen 3 IP hasn't been fully utilized yet.

An 18 months release cycle would put Zen 4 to Q2 2022. However, Zen 4 brings a brand new platform with DDR5/PCIe5. So delays are to be expected.

I guess we will have a "XT" refresh in Q3/4 2021 to refresh the media coverage.

Threadripper 5000 is coming in August. Warhol is definitely NOT an XT refresh.

The biggest shortage right now is substrates. And it takes the same sized substrate for a cheap $99 AM4 APU as it does for a 5950X. Assembly labor is also in shortage thanks to COVID. It really doesn't make sense right now to target the bottom of the market.

AMD has made a significant investment in this area. They now have a supply chain exclusive to them. They stated as much during earnings.

The leakers that claimed Warhol was cancelled and are now claiming this appear to be trolls.

My money is on Warhol shipping December.

 

[yuri69]

My first question would be if the Zen4 design has been completed by now because in last October it wasn't.

It was supposedly taped-out approximately in August 2020. So yeah, it's been design complete for a while. They are iterating on spins to get it ironed out for mass production.

 

[DisEnchantment]

https://finance.yahoo.com/video/amd-ceo-goal-bring-best-133833227.html

In case some one is still flip flopping (like me)... directly from Lisa Su (In the video around 4m mark)

We're very excited about our next generation which is our 5nm roadmap, we're committed to have that in the market in 2022

 

[B-Riz]

Threadripper 5000 is coming in August. Warhol is definitely NOT an XT refresh.

AMD has made a significant investment in this area. They now have a supply chain exclusive to them. They stated as much during earnings.

The leakers that claimed Warhol was cancelled and are now claiming this appear to be trolls.

My money is on Warhol shipping December.

I think another November launch would be really smart, to allow for Zen3 products to be discounted for the holiday buying season; with all the early adopters getting Warhol then.

 

[Det0x]

Dont know where to post it, but i guess this is as good place as any..

Sony Reportedly Prepping PS5 With 6nm AMD CPU

According to a report on DigiTimes, Sony's manufacturing partners are preparing to start production of a redesigned PlayStation 5 model in about a year from now. The new model is expected to be cheaper to build, which will enable the company to cut the price of its latest console, which is in line with typical strategy to cut a console's price after two years on the market. The redesigned unit is projected to have a shorter lead time, which should improve supply.

The new version of Sony's PlayStation 5 will reportedly rely on an AMD-designed system-on-chip (SoC) made using TSMC's N6 (6 nm) fabrication process as opposed to the current SoC which uses TSMC's N7 technology. Sony did not comment on the information to Digitimes. From the article, it appears the redesign is more internal, rather than changing the console's physical appearance.

Siliconware Precision Industries (SPIL), a part of ASE Technology Holding, and Tongfu Microelectronics are projected to continue providing chip packaging services for Sony's assembly partners. Meanwhile, no company has officially confirmed its involvement with a redesigned PS5.

TSMC's N6 process uses extreme ultraviolet lithography for up to five layers which allows the use of multipatterning, speeding up manufacturing and potentially increasing yields. Also, the N6 technology promises up to 18% higher transistor density compared to N7, which can shrink die size and further reduce costs. Meanwhile, N6 continues to use the same design rules as N7 and enables designers of SoCs to re-use the same design ecosystem (e.g., tools, IP), which drops development costs.

 

[Mopetar]

Dont know where to post it, but i guess this is as good place as any..

Sony Reportedly Prepping PS5 With 6nm AMD CPU

It's a little unusual to see them go for a die-shrink this quickly, but I suppose it could be just as much about getting additional wafer capacity as it is about cost savings.

It looks like they're still basically selling out immediately and the it looks like the eBay scalper price hasn't come down much if at all either.

 

[CakeMonster]

Sounds like a very good strategic move, with the same performance it will be cheaper to build as well as less risky in terms of cooling and failures.

I very much doubt there will be a better performing revision this early.

 

[eek2121]

It was supposedly taped-out approximately in August 2020. So yeah, it's been design complete for a while. They are iterating on spins to get it ironed out for mass production.

Note that post claims the die is 80mm2 on 5nm. Zen 3 on 7nm was roughly 84mm2.

https://finance.yahoo.com/video/amd-ceo-goal-bring-best-133833227.html

In case some one is still flip flopping (like me)... directly from Lisa Su (In the video around 4m mark)

That doesn’t tell us much. A November or December launch would basically mean 2022 availability.

I think another November launch would be really smart, to allow for Zen3 products to be discounted for the holiday buying season; with all the early adopters getting Warhol then.

I agree, not only that, but if Intel does manage to get Alder Lake out this year, AMD will need to be able to respond.

It's a little unusual to see them go for a die-shrink this quickly, but I suppose it could be just as much about getting additional wafer capacity as it is about cost savings.

It looks like they're still basically selling out immediately and the it looks like the eBay scalper price hasn't come down much if at all either.

18% smaller chip means 18% more chips per wafer, excluding yield differences.

 

[jpiniero]

18% smaller chip means 18% more chips per wafer, excluding yield differences.

Who knows what TSMC is charging for the N6 wafers compared to N7, plus the costs to pay AMD to shrink it. Maybe the difference won't be so bad a year from now?

I agree that it almost has to be a supply thing.

 

[Mopetar]

18% smaller chip means 18% more chips per wafer, excluding yield differences.

Is it a case where they could use the 7nm wafers that they already have with this new process or would they need to purchase separate/new wafers for it? If it's the later, it seems unlikely that they'd be less supply constrained as a result unless they could get at least the name number of wafers, or enough to compensate for the additional chips minus yield differences. That also assumes there aren't additional costs for the 6nm wafers over the 7nm ones which further offset any gains.

Some of the article makes it seem like this new node is just and updated 7nm with a new name, but I haven't been following it closely enough to know if that's the case.

 

[eek2121]

Is it a case where they could use the 7nm wafers that they already have with this new process or would they need to purchase separate/new wafers for it? If it's the later, it seems unlikely that they'd be less supply constrained as a result unless they could get at least the name number of wafers, or enough to compensate for the additional chips minus yield differences. That also assumes there aren't additional costs for the 6nm wafers over the 7nm ones which further offset any gains.

Some of the article makes it seem like this new node is just and updated 7nm with a new name, but I haven't been following it closely enough to know if that's the case.

6nm is 7nm with EUV. In theory it should be cheaper because of EUV.

 

[Mopetar]

6nm is 7nm with EUV. In theory it should be cheaper because of EUV.

Well cheaper relative to making a new product with 7nm. If it's porting an existing product that upfront cost was already paid. Then it's just a matter of whether paying a new upfront cost for the design changes and new masks is worth the cost savings or additional gains from the increased volume. For Sony it almost certainly would be because they're going to be making PS5 consoles for some time now.

 

[andermans]

Note that post claims the die is 80mm2 on 5nm. Zen 3 on 7nm was roughly 84mm2.

Note the that is in line with later leaks (

https://twitter.com/x/status/1366393857089409030

) which also claim the CCD is 8 cores again. Probably the cores didn't shrink that much due to additions to the cores and SRAM (used a lot in the L3 cache) not scaling as well.

 

[tomatosummit]

Well cheaper relative to making a new product with 7nm. If it's porting an existing product that upfront cost was already paid. Then it's just a matter of whether paying a new upfront cost for the design changes and new masks is worth the cost savings or additional gains from the increased volume. For Sony it almost certainly would be because they're going to be making PS5 consoles for some time now.

N6 is also design compatible with N7 so I don't think they need to remake any masks so moving to n6 isn't as much of an investment compared to n5 or even N7p, tsmc stated it's 7nm process is a long lasting process and n6 is going to be the best option for cusomers going forwards. It's probably similar to zen1 -> zen1+ on 14nm -> 12nm.

Sony can move to N6 and not take advantage of the density gains. Instead gain improved yields from both the euv layers and better performance of the process, the performance characteristics might be important as sony did clock the apu higher than anticipated originally.

I'd also guess it's a similar situation for the zen3 ccd (warhol?) and cezanne (barcelo?) on N6.

 

[dr1337]

*snip*

Well, apple managed to double cache on the a14 coming from the a13, on top of core improvements all while being 10% smaller. And that was jumping from n7p to n5. So AMD could be doubling l3 cache again, or maybe doubling l2 cache, and that would partially explain the leaked die size. But theres also like a million other things they could do to make the die bigger. More cores, way bigger cores, completely different layout/structure, ect.

 

[soresu]

Probably the cores didn't shrink that much due to additions to the cores and SRAM (used a lot in the L3 cache) not scaling as well.

I used to assume the same about cache but supposedly it scales pretty well on modern processes.

I think IO is the main part that does not scale well in any processor.

 

[soresu]

Do we have a better idea whether the process node for Zen4 CCD is N5 or N5P yet?

 

[jpiniero]

Well, apple managed to double cache on the a14 coming from the a13, on top of core improvements all while being 10% smaller. And that was jumping from n7p to n5. So AMD could be doubling l3 cache again, or maybe doubling l2 cache, and that would partially explain the leaked die size. But theres also like a million other things they could do to make the die bigger. More cores, way bigger cores, completely different layout/structure, ect.

How about SMT4?

 

[eek2121]

Do we have a better idea whether the process node for Zen4 CCD is N5 or N5P yet?

Not that I am aware of, but apparently the IOD is 6nm.

 

[andermans]

I used to assume the same about cache but supposedly it scales pretty well on modern processes.

I think IO is the main part that does not scale well in any processor.

AFAIU density improvement for SRAM on N5 vs. N7 is 30%, which is admittedly better than the shrinking of the CCD but still much lower than the logic.

 

[Mopetar]

N6 is also design compatible with N7 so I don't think they need to remake any masks so moving to n6 isn't as much of an investment compared to n5 or even N7p, tsmc stated it's 7nm process is a long lasting process and n6 is going to be the best option for cusomers going forwards. It's probably similar to zen1 -> zen1+ on 14nm -> 12nm.

Sony can move to N6 and not take advantage of the density gains. Instead gain improved yields from both the euv layers and better performance of the process, the performance characteristics might be important as sony did clock the apu higher than anticipated originally.

Wouldn't you need to make new masks to use EUV? My understanding is that with EUV it requires fewer layers/masks compared to the existing techniques, but is it actually possible to reuse the older masks, or a subset of them rather, without any unintended consequences? Also, it seems wasteful not to take advantage of the extra 18% density, particularly when everyone is supply constrained.

 

[tomatosummit]

Wouldn't you need to make new masks to use EUV? My understanding is that with EUV it requires fewer layers/masks compared to the existing techniques, but is it actually possible to reuse the older masks, or a subset of them rather, without any unintended consequences? Also, it seems wasteful not to take advantage of the extra 18% density, particularly when everyone is supply constrained.

Good point on the masks, I'm just going off tsmc themselves saying it's design compatible. It would depend on how much it would cost to redo the design for the shrink, what seems quite simple might be tens of millions of dollars and a significan't time line with qualification steps compared to theoretically making new masks from the old design. As far as I'm aware these masks aren't permanant either and do degrade or expire and would need to be remade in the future.
There are advantages for sony to the n6 node even if you don't make any space saving into account, especially in the yield from binning/performance characteristics because of the rumours of the overclocking they required.

 

[mikk]

Genoa's shipping already, so. Unless you think Raphael is going to be radically different . . . you have your answer.

Do you have a source?

It was supposedly taped-out approximately in August 2020. So yeah, it's been design complete for a while. They are iterating on spins to get it ironed out for mass production.

This can't be true because AMD told that Zen4 is in design last October. Don't trust every rumor.