Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[bsp2020]

Can somebody tell me what's the opposite of paper launch is called?

Diamond launch? https://seekingalpha.com/instablog/...-hands-boomer-s-guide-to-wallstreetbets-lingo

 

[soresu]

Can somebody tell me what's the opposite of paper launch is called?

A hard launch.

I've sometimes heard a paper launch called a soft launch.

Double entendre because it is indeed hard to do.

Even in normal times minus the current fab crunch.

 

[eek2121]

OK, since Milan was ready and shipping back in 2020. Why did AMD delay the launch? They delayed it so much it didn't make the announced 2020 release by almost a quarter. All those "2020 Milan" roadmaps were useless - even those presented even in March 2020...

The Milan delay hurt AMD's PR image of a rock-solid roadmap execution.

Man you guys are nuts. From the point a chip enters mass production until the point it is released can be anywhere from 6-24 months. That is why it blew my mind to see people going nuts when Intel said that ADL-S is entering mass production later this year. Even absent a pandemic or chip shortage, these things don't happen overnight. The closer you are to leading edge, the lower the capacity and the longer it takes to ramp up.

 

[leoneazzurro]

Man you guys are nuts. From the point a chip enters mass production until the point it is released can be anywhere from 6-24 months. That is why it blew my mind to see people going nuts when Intel said that ADL-S is entering mass production later this year. Even absent a pandemic or chip shortage, these things don't happen overnight. The closer you are to leading edge, the lower the capacity and the longer it takes to ramp up.

Yep. And that time is even longer when server platforms are involved, even if as a socket Milan is a drop-in replacement of Rome at socket level. it is, but certification, tests, and debugging are on a completely other level. And this must be accomplished with more than one partner. By the way, there were news about Milan chips already shipping in 2020 to "selected partners", possibly the supercomputer projects.

 

[uzzi38]

possibly the supercomputer projects.

Cloud vendors

 

[DrMrLordX]

OK, since Milan was ready and shipping back in 2020. Why did AMD delay the launch?

ODM sales are huge. Gone are the days when Intel has to partner with someone like Dell to sell everything "above board" through corporate portals/online catalogs. AMD likely had the opportunity to sell every Milan they could crank out to ODMs alone for months and months, so they didn't launch the product above-board because . . . why? They weren't going to bother supplying anything to smaller players. Milan's launch represents the point where AMD had finally saturated ODM demand with product.

 

[soresu]

Even absent a pandemic or chip shortage, these things don't happen overnight.

Or fab node problems.

I don't think 10nm is yet up to speed capacity wise vs 14nm+++++++.

 

[jamescox]

For Warhol to be at 15%+ of Vermeer while still being on DDR4, it would need some significant cache improvements. 6nm isn't a major density improvement, so the change would likely have to relate to cache latencies. Maybe they will expand the L2 cache a bit.

Isn’t is supposed to be 15 to 18% density improvement? That seems like good scaling considering scaling is getting very difficult. I don’t know how many extra chips per wafer that is; hopefully it will help fill demand though. Higher density isn’t great for cooling, so they may not shrink it that much. It may need to have some extra dark silicon to prevent hot spots.

If they have a new IO die, even if it is still meant to use DDR4, then that could increase performance significantly. I don’t know why they would make a new IO die for DDR4 unless it can connect to DDR5 also. AMD does go for very modular design though, so it may be that they can easily make a new, improved IO die without that much work. It still seems like it would be a very short lived product if it isn’t reusable for Zen 4 / AM5 products. I don’t know how plausible it is to have an IO die support both DDR4 and DDR5. The pci-express should be backward compatible though.

If they do have an IO die on a more advanced process, then that could reduce package power a bit. I have been expecting infinity cache to make it into Epyc eventually. I guess it is possible that a new IO die on TSMC could have L4 cache in the IO die or have other improvements to reduce latency. They could upgrade the connection between cpu and IO die also. Going up to pci-express 5 speeds just for IO die to CPU connections would make even more sense if the IO die has cache on it. Pci-express 5 isn’t really needed in the consumer market though. It would be interesting if it actually is a stacked device with cache stacked on top. Something like that is expected for Epyc eventually (an active interposer). It seems like they have quite a few opportunities for improvement that do not involve much core changes.

It is hard to tell what kind of bottlenecks exist within the core. It is possible that there are some inefficiencies in the new 32 MB L3 that could be fixed with minor changes. If it is going to be ryzen 6000 rather than 5000 XT, then it may have significant improvements. I have seen a lot of people using Ryzen 7000 for Zen 4, but I don’t know if there is any real information on that.

 

[dnavas]

I don’t know why they would make a new IO die for DDR4 unless it can connect to DDR5 also.

They'd do that if they have improved the power efficiency of the IO die. If the X570S is really more efficient, it's possible there have been similar improvements to the IO die.

Aside from DDR5, you could also slip pcie 5 in there as you suggest further down -- maybe AMD doesn't want Intel shipping pcie5 before they do? It's a lot easier to deal with compatibility when you're the one shipping the implementation that the other guy has to be compatible with....

I would think that move would make more sense in the TR market where the need for a new socket is more pressing (maximum power delivery), you can justify it by claiming it's required by pcie5, there's a group of people who will pay for it, and it's probably the only market that will make use of it (aside from the server market). It's also possible that work on pcie5 is what led to better power efficiency for pcie4 (and that could be true independent of whether they're aggressively upgrading interconnectivity).

 

[eek2121]

Or fab node problems.

I don't think 10nm is yet up to speed capacity wise vs 14nm+++++++.

They also have at least 3 different variants of 10nm.

 

[LightningZ71]

And according to their latest financials, TSMC uses none of them.

 

[Saylick]

A hard launch.

I've sometimes heard a paper launch called a soft launch.

Double entendre because it is indeed hard to do.

Even in normal times minus the current fab crunch.

If your hard launch lasts for more than 4 hours, immediately see your nearest doctor.

Explains why we never get one any more...

 

[Doug S]

I don’t know why they would make a new IO die for DDR4 unless it can connect to DDR5 also.

DDR5 is going to scarce and expensive at first, like any new memory standard. Any new I/O die coming out in the next three years MUST support DDR4.

 

[Tuna-Fish]

DDR5 is going to scarce and expensive at first, like any new memory standard. Any new I/O die coming out in the next three years MUST support DDR4.

Lol no. You cannot reasonably do both in a single one without being really inefficient, because there is no reasonable way of putting both the standards through the same socket. What you do is you make one IO die that does only DDR5 and one that does only DDR4, and sell the former in AM5 cpus and the latter in AM4 ones, potentially with the same ccd.

 

[jpiniero]

Lol no. You cannot reasonably do both in a single one without being really inefficient, because there is no reasonable way of putting both the standards through the same socket. What you do is you make one IO die that does only DDR5 and one that does only DDR4, and sell the former in AM5 cpus and the latter in AM4 ones, potentially with the same ccd.

Dunno, Alder Lake is expected to support both. Now the board would presumably work with only one or the other so you would have to choose.

 

[Tuna-Fish]

Dunno, Alder Lake is expected to support both. Now the board would presumably work with only one or the other so you would have to choose.

without being really inefficient

There's a reason why the previous socket had 1200 pins and alder lake has 1700.

 

[jamescox]

Lol no. You cannot reasonably do both in a single one without being really inefficient, because there is no reasonable way of putting both the standards through the same socket. What you do is you make one IO die that does only DDR5 and one that does only DDR4, and sell the former in AM5 cpus and the latter in AM4 ones, potentially with the same ccd.

If it is plausible, then I would expect that the silicon would support both, but once it is in a package, it would be limited to one or the other. I don’t think there would be a board with both DDR4 and DDR5 slots, if that is what you were thinking of. I would expect two different packages, one with DDR4 pins routed and one with DDR5 pins routed. I thought they were electrically incompatible, so I don’t know if they can do switchable pins like they do for all of the different IO types and cpu links. Those pretty much all use pci-express physical layer with different protocols running on top.

I am thinking that a Zen 3+ (If it exists) might have some tweaks to the L3 cache and everything else will probably be IO die improvements in some manner. Even just higher clocks on the IO die could allow them to reduce latency. I assume they need much higher clocks to support DDR 5 properly anyway. They need much higher clocks or much wider internal interconnect to keep up with pci-express 5 speeds if it is used for the IO die to cpu connection.

 

[Timorous]

DDR5 is going to scarce and expensive at first, like any new memory standard. Any new I/O die coming out in the next three years MUST support DDR4.

Nah. Just have AM4 and AM5 both available so budget stuff can be Zen 3+ / AM4 / DDR4 and higher end stuff can be Zen 4 / AM5 / DDR5.

 

[jamescox]

DDR5 is going to scarce and expensive at first, like any new memory standard. Any new I/O die coming out in the next three years MUST support DDR4.

The old IO die can probably be used with newer versions of the cpu die as long as it still uses a compatible interface, so I don’t know if that is true. It seems like they could have one part with Zen 3(+) using existing DDR4 IO die and another part with Zen 3(+) and a new DDR5 IO die. If they make an updated part supporting DDR4, then it might be one last upgrade for AM4. It is like using two different north bridges for the same cpu, so I am kind of leaning towards a new IO die not supporting DDR4. It is kind of funny that current Ryzen block diagrams look about the same as the initial dual socket Athlon with EV6 bus from 1999. You get 8 cores instead of 1, but the point to point links and “IO die” are just about the same.

AMD Athlon

www.anandtech.com

Actually written by Anand. I did read Anandtech back in 1999, so I probably read that as soon as it came out. Was probably reading it on an AMD k6-2 at home or possibly a SPARC station at work; don’t remember.

 

[Timorous]

The old IO die can probably be used with newer versions of the cpu die as long as it still uses a compatible interface, so I don’t know if that is true. It seems like they could have one part with Zen 3(+) using existing DDR4 IO die and another part with Zen 3(+) and a new DDR5 IO die. If they make an updated part supporting DDR4, then it might be one last upgrade for AM4. It is like using two different north bridges for the same cpu, so I am kind of leaning towards a new IO die not supporting DDR4. It is kind of funny that current Ryzen block diagrams look about the same as the initial dual socket Athlon with EV6 bus from 1999. You get 8 cores instead of 1, but the point to point links and “IO die” are just about the same.

AMD Athlon

www.anandtech.com

Actually written by Anand. I did read Anandtech back in 1999, so I probably read that as soon as it came out. Was probably reading it on an AMD k6-2 at home or possibly a SPARC station at work; don’t remember.

Yea chiplets + io die is just CPU + NB on a single package with a better FSB.

I don't see Zen 4 + DDR4 IO Die though because it could be confusing for users and perhaps they want to do some things with Zen 4 that they can't on AM4 due to the current spec. Also Zen 4 will be on 5nm so I expect AMD will want to maximise ASP on that product line and any DDR4 offerings would be somewhat budget friendly versions.

I really do expect Zen 3+ and Zen 4 to be available at the same time for quite a while as it allows AMD to sell a more budget friendly product that won't cannibalise the higher performing parts because I anticipate that there will be a distinct difference in terms of performance.

 

[Tuna-Fish]

If it is plausible, then I would expect that the silicon would support both, but once it is in a package, it would be limited to one or the other. I don’t think there would be a board with both DDR4 and DDR5 slots, if that is what you were thinking of. I would expect two different packages, one with DDR4 pins routed and one with DDR5 pins routed. I thought they were electrically incompatible, so I don’t know if they can do switchable pins like they do for all of the different IO types and cpu links. Those pretty much all use pci-express physical layer with different protocols running on top.

If they do that, why not just have two separate IO dies with different memory controllers?

 

[lobz]

If they do that, why not just have two separate IO dies with different memory controllers?

Because that way if you wanted upgrade to another board and ddr5, you'd have to buy a new CPU as well. Kinda goes against what AMD's been trying to sell about themselves.

 

[jpiniero]

There's a reason why the previous socket had 1200 pins and alder lake has 1700.

Couldn't you just reconfigure how the pins output? You're only going to use one or the other. Either way just supporting both with AM5 seems to be the way to go.

 

[scineram]

If they do that, why not just have two separate IO dies with different memory controllers?

Well, that could be what Warhol is. I hope.

 

[jamescox]

Yea chiplets + io die is just CPU + NB on a single package with a better FSB.

I don't see Zen 4 + DDR4 IO Die though because it could be confusing for users and perhaps they want to do some things with Zen 4 that they can't on AM4 due to the current spec. Also Zen 4 will be on 5nm so I expect AMD will want to maximise ASP on that product line and any DDR4 offerings would be somewhat budget friendly versions.

I really do expect Zen 3+ and Zen 4 to be available at the same time for quite a while as it allows AMD to sell a more budget friendly product that won't cannibalise the higher performing parts because I anticipate that there will be a distinct difference in terms of performance.

I agree. I would expect Zen 4 to be DDR5 only. They don’t want to be selling a crippled version. I could see them making a Zen 3+ that supports both somehow. It seems more likely that it would be the old DDR4 IO die (still 5000 series) or a new IO die (perhaps 6000 series) that probably only supports DDR5 and can probably be used with Zen 3+ or Zen 4. It doesn’t seem like they need to make the AM5 IO die support DDR4; just use the old one. The cpu to IO die link should be backward compatible since it is essentially pci-express physical layer. I was expecting them to move to stacked chips at some point, which might use a completely different physical interface. Perhaps that doesn’t happen with initial Zen 4 though.