Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

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Vattila

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Oct 22, 2004
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Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

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What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts! :)
 
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uzzi38

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Oct 16, 2019
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i know that! ;) question is ... is he/she a known leaker?

Nope. But everyone has to start somewhere.

Not like I can accurately validate every rumour, so I can't possibly vouch for/against the guy without seeing if enough of what he says is accurate.

Ultimately at the end of the day though - it's a rumour and you should treat it as such. It's your choice whether or not you want to believe it, but the best choice is almost always for wait for more information.
 
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Ajay

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https://chipsandcheese.com/2021/02/05/amds-past-and-future-cpus/ popped up on Reddit...

Zen 4: "over 25% IPC gain" (up to 40%, Genoa 29% faster than Milan with same number of cores)
Zen 5: jump as large as from Piledriver to Zen 1. Zen 5’s original design goal was 2.5 to 3 times the IPC of Zen 1

:oops:
Bollocks!
so please take all information in this section with the usual grain of salt.
Nah, a shaker full of salt.

Zen 3+ looks to be a small IPC gain on base Zen 3, I have been told “It’s more than Zen+ was but not much” which I interpret to mean around a 4 to 7% IPC gain along with clock gains because Zen 3+ is on the N6 node from TSMC
N6 for Zen3+ either bollocks, or Zen4 is running late. AMD would probably want at least a year worth of sales to justify new masks.

Zen 4 is what a lot of people are waiting for, and well, the info I have will make that wait even more worth it. I have heard many things about Zen 4, all of which is positive. Over 25% IPC gain, total performance gain of 40%, possibly 5GHz all core because of the new N5 node from TSMC!
25% increase in throughput per clock - possible, but that's going to takes some really clever engineering - density improvements from N7 to N5 aren't looking good so far. Another 15% due to clocks - N5P would have to be a miracle node, still using FinFETs which are seeing diminishing returns on shrinks at this point.

The Zen5 'rumors' must be pure speculation - unless this guy has a direct line to Mike Clark.
 

Zepp

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May 18, 2019
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Zen 5: jump as large as from Piledriver to Zen 1. Zen 5’s original design goal was 2.5 to 3 times the IPC of Zen 1

Almost fell out of my chair at just the possibility of this being true. I've been so used to relatively small CPU performance increases in the last 15 years I've been thinking we were nearing an end to large IPC jumps on current tech.
 
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dr1337

Senior member
May 25, 2020
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The Zen5 'rumors' must be pure speculation - unless this guy has a direct line to Mike Clark.
I think its entirely speculation, Their website came out of nowhere only a few months ago and all of their other articles are just dissertations with cited sources, usually from other leakers. IDK maybe they really do have someone high up on the inside dripping info on them but its just too simple and easy enough to write off as speculation. I mean, the only reason anyone thinks zen3+ even exists is that one "leaked" roadmap from months ago, so to me it really just looks like they're putting their hot takes onto it.
 

uzzi38

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Oct 16, 2019
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N6 for Zen3+ either bollocks, or Zen4 is running late. AMD would probably want at least a year worth of sales to justify new masks.

Thus far leaked roadmaps have pegged Rembrandt to be Zen 3+ on N6. Although I know this portion of the article is about Warhol, just pointing out Zen3+ on N6 isn't new.
 

gdansk

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Feb 8, 2011
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https://chipsandcheese.com/2021/02/05/amds-past-and-future-cpus/ popped up on Reddit...

Zen 4: "over 25% IPC gain" (up to 40%, Genoa 29% faster than Milan with same number of cores)
Zen 5: jump as large as from Piledriver to Zen 1. Zen 5’s original design goal was 2.5 to 3 times the IPC of Zen 1

:oops:
If Zen 5 is super-wide monster, one may expect it to clock lower. I expect AMD to go that direction at some point but who knows if this guy is simply throwing things at the wall or has a source.
 

LightningZ71

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Mar 10, 2017
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Given how aggressive the competition is in the mobile space, I won't be shocked if we get more designs and products then we would otherwise expect. The density increase on N5 would be most useful in the server arena just so they can fit more CCDs on their EPYC packages. N6, being a further refinement of N7, and a "less comprehensive" engineering hurdle from N7 to target, would make sense for the continued reuse of N7 based products, such as RDNA2, and a tweak of Zen3 (to be +). Just modest improvements on Cezanne should keep AMD competitive at worse with whatever Intel will produce in the mobile space in the next year, as Tiger Lake H (8c) won't be significantly faster in single core, and I speculate will have thermal/power limits vs. Cezanne that will keep its MT performance within reach. N6 based Rembrandt, assuming that it is real, should be competitive.

With N5 not (expected to be) clocking higher, it makes sense that Zen4 would go wider for more performance, as density, while not amazingly better, is still up enough to keep die sizes reasonable with wider cores.
 
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inf64

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Zen5 should have the same IPC goal as any of AMD's "tocks". The goal was 40% versus previous tock.
So tocks were/are/will be : Zen1, Zen3, Zen5.

Zen1 -> Zen3 has brought us : 1.035(Zen+) x 1.15 (Zen2) x 1.19 (Zen3) = 1.41 or ~40%
Zen3 -> Zen5 will mots likely be something like this : 1.03 (Zen3+?) x 1.15 (Zen4?) x 1.2 (Zen5?) = 1.42 or 42%

This seems entirely plausible based on the past iterations of Zen core and most likely scenario. Note that this is only the ST IPC in core vs core scenario, I didn't count in the clocks(to increase 10-15% vs Zen3), core counts (most likely to double versus Zen3), FP improvements (AVX 512 is a given with either Zen4 or Zen5).

All in all, I personally think that AMD is positioned really well to remain the x86 marke leader no matter what Alder Lake brings. AL might regain slight IPC edge versus Zen3/Zen3+ but Zen4 will bring that leadership back easily and Zen5 will further cement it. Zen5 VS Meteor Lake will most likely be a reprise of Milan versus Icelake, no competition really.
 

exquisitechar

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Apr 18, 2017
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You just know they are clueless when they talk about N5 clock gains.
Why is that? From what I've read, N5 is really good in that regard. Of course, that doesn't mean that we'll be seeing 5GHz all core, especially since Zen 4 is a new core. There may even be a decrease in clock speeds depending on what changes AMD makes.

The IPC increase claim for Zen 5 certainly sounds pretty nuts, but I wouldn't be surprised much at all if Zen 4 was an over 20% increase over Zen 3. Not the first time I've seen such a figure.
 

Ajay

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Zen1 -> Zen3 has brought us : 1.035(Zen+) x 1.15 (Zen2) x 1.19 (Zen3) = 1.41 or ~40%
Zen3 -> Zen5 will mots likely be something like this : 1.03 (Zen3+?) x 1.15 (Zen4?) x 1.2 (Zen5?) = 1.42 or 42%
So, that could be the same way these cheese people estimated Zen5 performance. If AMD can maintain these double digit uplifts every other chiplet, I suppose it's possible. I think, at this point, it depends on how much die space AMD is willing to use. With actual area shrinks declining (stuck on FinFET - down to 3N @ TSMC), AMD may not be able to shrink chiplet sizes much inorder to add a larger front end, Ex units and add larger buffers etc. I would think hitting that level of throughput on Zen5 would require more cache as well.
 

soresu

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Dec 19, 2014
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N6 for Zen3+ either bollocks, or Zen4 is running late. AMD would probably want at least a year worth of sales to justify new masks.
Predicted node capacity crush on N7/N7P may well have prompted the N6 move, even if the gains in perf are insubstantial.
 

moinmoin

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Predicted node capacity crush on N7/N7P may well have prompted the N6 move, even if the gains in perf are insubstantial.
Usually the newer nodes experience more capacity crush since capacity first has to be built up to begin with, and N7/N7P should be further along with capacity expansion. The case for N6 is even more complex due to its extensive use of scarce EUV machines that should be better used for N5.
 

Panino Manino

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I remember when people didn't believe in the Zen 1 IPC and where surprised, but this is different, count me in on those in disbelief.
I don't believe ANY chip maker will achieve these ludicrous jumps.
 

Hans Gruber

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I remember when people didn't believe in the Zen 1 IPC and where surprised, but this is different, count me in on those in disbelief.
I don't believe ANY chip maker will achieve these ludicrous jumps.
Whether you believe it or not. When AMD introduced Ryzen they had a roadmap up to Zen 4. Anything beyond is new architecture beyond the original Ryzen platform.
 

eek2121

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Predicted node capacity crush on N7/N7P may well have prompted the N6 move, even if the gains in perf are insubstantial.

It would not surprise me if they moved to N6. By delaying a year for 5nm, it gives them time to:
  • Wait for TSMC to expand 5nm capacity
  • Give time for Apple to get OFF 5nm and onto a smaller node.
I speculate we'll see a mix. Low volume, high margin, high performance parts will hit 5nm. Lower margin, lower performance parts will hit 6nm. I have no idea how that would work, but with laptops we already have a mix of Zen 3 + rehashed Zen 2 chips. It would not surprise me to see a mix of 5nm and 6nm chips for Ryzen 6000. Sure, there is a bit of increased upfront cost, but if they could substantially raise volume, they'd more than make up for it.
 
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Thibsie

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I'm not quite sure Apple will leave 5nm for quite a time. They mau lower wafer orders though but Intel certainly won't order 7nm either so we still don't know how capacity availability will evolve IMO.

Anyway, it is in all parties interest (even TSMC IMO) to have Samsung able to compete with TSMC. Sooner the better.
 

moinmoin

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I'm not quite sure Apple will leave 5nm for quite a time. They mau lower wafer orders
Apple won't leave nor lower wafer orders, the node usage is just being carried through the whole Apple products stack until its usage of a given node ceases.

But that doesn't mean Apple's share of the whole node capacity doesn't reduce over time. It does, because Apple only "hogs" the majority of the initial capacity, the capacity of phase 1. TSMC always plans to expand a node's capacity in at least 3 phases, if not more. The limiting factor there may be the scarcity of EUV machines (which is why I don't expect N6 to be a big node at first).