Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[randomhero]

What a shame glofo bowed out of 7nm,their fabs would be at 100% now. Even 1 year late to the game.
But hindsight is 20/20.

 

[randomhero]

Given that no one seems to be able to match TSMC currently, TSMC‘s production capacity is going to stay in short supply just due to demand. If AMD sticks with 32 MB L3 for Zen 4, which I think makes sense, the CCD die will be very small even without much of a shrink. They may move to larger L2 caches in some manner. Apple does very well with large, shared L2, although that sharing generally isn’t going to scale to a large number of cores. Intel went with large shared L3 with Nehalem at 4-cores. The previous core 2 duo processors with large L2 shared between 2 cores still does very well for some applications. I still use a core 2 duo based 17 inch MacBook Pro (the last 17 inch MacBook Pro). It is unclear if they will just increase L2 size, or re-architect it a bit. I am wondering if it would actually make sense to go back to 2 cores sharing a single larger L2, then from the L3 perspective, it looks somewhat like a 4 core CCX again. That would make very efficient use of resources, but it may affect software scheduling optimizations again.

The current CCD is only around 75 square mm, which is probably smaller than most mobile chips which include a gpu and a bunch of other fixed function hardware. They may reduce the die size by moving to chip stacking of some form so they will not need 32-bit (single direction) serdes links between CCD and IO die. Increasing the L2 cache sizes may increase the die area slightly, but it may not be significant due to the node shrink. If they share the L2 among 2 cores or something, then that could allow them to be much more efficient on die area. At 5 nm they may be able to add a lot of functionality with minimal increase in die size.

They would still want to sell the CCD in the higher mid-range and high end desktop parts. Basically, they make massive numbers of CCD, which isn’t hard to do given the number of die per wafer at such a small size. The higher leakage, higher clocking die go to the desktop market where a 65 watt 6-core is okay. The lower leakage parts get stockpiled for Epyc. There is a good chance that the Ryzen CCDs just aren’t good enough to be Epyc processors except for some of the weird 2 CCD Epyc parts. The 5950x may be be one high leakage, high clock die paired with a lower leakage, more Epyc-like die (higher price). Given the pricing structure, they want you to buy the 6-core or the 12-core, which are probably both not good enough power consumption bin for Epyc.

I don’t think we are going to see increased L3 with Zen 4. It just doesn’t really seem to make much sense. The latency penalty would be high, but I guess larger L2 could make up for it, so I guess we can’t rule it out. They could make multiple types of CCD eventually. They could use a 64 MB CCD for high end database applications and HPC, but I don’t know if it would be necessary if Epyc gets L4 (infinity cache). I don’t think they would add L4 cache to the desktop IO die; 32MB is already huge. We may see some more APUs in the desktop market and those could be candidates for staying on 7 nm or 6 nm while leaving the 5 nm allocation for Genoa CCD with essentially salvage CCD for high-end desktop. Zen 3 is pretty much only higher end mid-range and high end desktop plus presumably stockpiles for Milan currently. We don’t have <300$ Ryzen 5000 yet; anything less than the 5600x might still be an APU.

While it makes perfect sense what are you saying, I'm still of opinion that N5 products will be for enterprise only.While now growth in market share for Epyc and CDNA seems slow, in 5 quarters IMHO floodgates will open. So i don't expect 5N products for consumers till late Q3 2022.

 

[Thibsie]

Good thing there's 6nm then.

 

[DrMrLordX]

What a shame glofo bowed out of 7nm,their fabs would be at 100% now. Even 1 year late to the game.
But hindsight is 20/20.

Too expensive. GF wasn't going to throw money at it, and there's no guarantee the process would've even worked.

 

[CakeMonster]

Given the pricing structure, they want you to buy the 6-core or the 12-core, which are probably both not good enough power consumption bin for Epyc.

Somewhat out of context, but wouldn't this mean AMD could benefit to go for CCX with more than 8 cores for a mass production product planned for release in late '21 or possibly '22? To allow for the cut down ones to cover more of the mainstream needs by then which is probably 8 core?

 

[jpiniero]

But by volume? Right now AMD is estimated to be using 45k wpm. That too constrained by supply.

45k wpm is crazy. That'd cost way more than AMD's entire revenue. That cant be right.

 

[Hitman928]

45k wpm is crazy. That'd cost way more than AMD's entire revenue. That cant be right.

At 8K per wafer that would be $360M per month or $1.08B per quarter. In the last quarter AMD had $2.8B in revenue and expects $3B in revenue for the current quarter. While I don't know exactly how accurate, 45K wpm seems like a reasonable estimate.

 

[DisEnchantment]

45k wpm is crazy. That'd cost way more than AMD's entire revenue. That cant be right.

In numbers, AMD would consume 21% share of TSMC’s 7nm wafer capacity with 30,000 WPM. HiSilicon and Qualcomm would be responsible for 17-18% share and MediaTek for 14%. This would leave 29% of TSMC’s 7nm capacity to the rest of its customers.

AMD to Become TSMC’s Largest 7nm Customer In 2020: Report

According to Apple Daily, AMD will become TSMC's largest 7nm customer in the second half of 2020, driven by a doubling in orders and Apple moving to 5nm.

www.tomshardware.com

“It’s not a problem for TSMC, since there is plenty of demand to reallocate that capacity, most likely filling more AMD demand,” Yao said

World's biggest chipmaker expected to absorb loss of Huawei business

World's biggest chipmaker expected to absorb loss of Huawei business

www.asiatimesfinancial.com

They have 30K wpm in Q2. And they got more from Q3 - Q4, they got a chunk of the Huawei Wafers. (Huawei's share in Q1-Q2 is around 18% which is close to AMD's 21% of N7 production, that is around 25-26 kwpm)
45k wpm is reasonable estimate.

If not for the consoles they would be making bank, sadly margin from console chips is "wafer" thin.

 

[jpiniero]

At 8K per wafer that would be $360M per month or $1.08B per quarter. In the last quarter AMD had $2.8B in revenue and expects $3B in revenue for the current quarter. While I don't know exactly how accurate, 45K wpm seems like a reasonable estimate.

Ah maybe I did the math wrong.

 

[moinmoin]

Good thing there's 6nm then.

N6 takes capacity from N7 since it's all built from the same base, so if N7 is capacity constrained N6 won't help with that. N5 is separate.

 

[bsp2020]

N6 takes capacity from N7 since it's all built from the same base, so if N7 is capacity constrained N6 won't help with that. N5 is separate.

I heard that using EUV will cut the number of steps necessary to make chips, reducing the production time. That in turn, can increase throughput using the same number of machines. Once TSMC receives more EUV machines, deploying them on 7nm process may improve throughput. I'm not too familiar with process technology. So, if someone on this board can elaborate, I'd appreciate it.

 

[jpiniero]

N6 takes capacity from N7 since it's all built from the same base, so if N7 is capacity constrained N6 won't help with that. N5 is separate.

AT's articles on the topic say that N6 does use different equipment.

 

[DisEnchantment]

I heard that using EUV will cut the number of steps necessary to make chips, reducing the production time. That in turn, can increase throughput using the same number of machines. Once TSMC receives more EUV machines, deploying them on 7nm process may improve throughput. I'm not too familiar with process technology. So, if someone on this board can elaborate, I'd appreciate it.

The following figure can give a good idea. Only N5 is having a real reduction in mask count.
However the reduction in mask count is accompanied with more time for the process steps related to EUV, so all in all there is no actual improvement.
There are many factors for this, the lower power of the laser is one of the problems with early machines.



N6 would largely be same in similar mask count to N7. According to Wikichip, there are 5 layers related to EUV in N6.
N7 has somewhere around 70-80 masks to complete a wafer, depending on the customer.
What they did for N6 was, instead of routing the wafers across the DUV machines entirely , Mostly TwinScan NX/T, on the fab floor, there are hops in between to the TwinScan NXE for the EUV steps.

Fab 18 is the only one producing N5, whereas N7 is produced mainly in 2 Giga fabs (Fab 14 and 15), and the 2 other fabs reportedly producing some amount with older EUV equipment, research fab 12B and fab 12A.

Looking at the shipment and order backlog for ASML EUV machines, it is terrible.

So the lesser machines are there, the more the mask switching happens which affects defect density and capacity.
N6 could take away some of the machines meant for N5.
Due to COVID both Samsung and TSMC had problems installing their newest NXE machines. This is public report.
This is my understanding based on publicly available sources.

 

[randomhero]

Too expensive. GF wasn't going to throw money at it, and there's no guarantee the process would've even worked.

Yeah, gambling away billions is not what sound businesses do. And going 7nm for glofo at the time was high risk(and investment) for low return or no return.

 

[randomhero]

The following figure can give a good idea. Only N5 is having a real reduction in mask count.
However the reduction in mask count is accompanied with more time for the process steps related to EUV, so all in all there is no actual improvement.
There are many factors for this, the lower power of the laser is one of the problems with early machines.

View attachment 35180

N6 would largely be same in similar mask count to N7. According to Wikichip, there are 5 layers related to EUV in N6.
N7 has somewhere around 70-80 masks to complete a wafer, depending on the customer.
What they did for N6 was, instead of routing the wafers across the DUV machines entirely , Mostly TwinScan NX/T, on the fab floor, there are hops in between to the TwinScan NXE for the EUV steps.

Fab 18 is the only one producing N5, whereas N7 is produced mainly in 2 Giga fabs (Fab 14 and 15), and the 2 other fabs reportedly producing some amount with older EUV equipment, research fab 12B and fab 12A.

Looking at the shipment and order backlog for ASML EUV machines, it is terrible.
View attachment 35181
So the lesser machines are there, the more the mask switching happens which affects defect density and capacity.
N6 could take away some of the machines meant for N5.
Due to COVID both Samsung and TSMC had problems installing their newest NXE machines. This is public report.
This is my understanding based on publicly available sources.

As always great info and summary. Tip of the hat.

 

[Doug S]

What we know are their roadmaps and interviews. We know Zen4 on N5 is planned. We know that they are going to use other N7 family nodes for future products. We know that they are working towards stacking from patents. We know that they still want to progress core counts. What we don't know are specifics.

You can't say that you "know" what they are working towards or will do based on patents. Companies patent all the paths they take during research/pathfinding for the future, so a patent doesn't tell you which path they eventually take.

Just look at Apple as an example (since the tech press seems to report on Apple's patents more than just about anybody) where they have patented a lot of things they haven't done (and one can conclude will never do in some cases, based on what they ended up doing instead)

 

[Doug S]

I heard that using EUV will cut the number of steps necessary to make chips, reducing the production time. That in turn, can increase throughput using the same number of machines. Once TSMC receives more EUV machines, deploying them on 7nm process may improve throughput. I'm not too familiar with process technology. So, if someone on this board can elaborate, I'd appreciate it.

EUV reduces the number of steps (no longer doing double or quadruple patterning) but the throughput of the EUV machines is less than the DUV machines they replaced - and the throughput of the EUV machines is lower enough it is still a loss in throughput overall.

They are slowly improving the wattage of the light source in EUV machines, so that won't be the case forever, but in another couple generations we're expected to have to start double patterning the lowest layers once again.

 

[Ajay]

The following figure can give a good idea. Only N5 is having a real reduction in mask count.
However the reduction in mask count is accompanied with more time for the process steps related to EUV, so all in all there is no actual improvement.
There are many factors for this, the lower power of the laser is one of the problems with early machines.

View attachment 35180

N6 would largely be same in similar mask count to N7. According to Wikichip, there are 5 layers related to EUV in N6.
N7 has somewhere around 70-80 masks to complete a wafer, depending on the customer.
What they did for N6 was, instead of routing the wafers across the DUV machines entirely , Mostly TwinScan NX/T, on the fab floor, there are hops in between to the TwinScan NXE for the EUV steps.

Fab 18 is the only one producing N5, whereas N7 is produced mainly in 2 Giga fabs (Fab 14 and 15), and the 2 other fabs reportedly producing some amount with older EUV equipment, research fab 12B and fab 12A.

Looking at the shipment and order backlog for ASML EUV machines, it is terrible.
View attachment 35181
So the lesser machines are there, the more the mask switching happens which affects defect density and capacity.
N6 could take away some of the machines meant for N5.
Due to COVID both Samsung and TSMC had problems installing their newest NXE machines. This is public report.
This is my understanding based on publicly available sources.

ASML's inability to scale with demand has been a disaster for EUV for advanced manufacturing nodes. The reduced mask count helps, but these machines are still slower than the DUV steps.
IIRC, TSMC's N5 isn't 100% EUV (and doesn't need to be anyway). Fab 18 would have a much higher capacity (wpm) if more EUV machines were available.

 

[moinmoin]

You can't say that you "know" what they are working towards or will do based on patents. Companies patent all the paths they take during research/pathfinding for the future, so a patent doesn't tell you which path they eventually take.

Just look at Apple as an example (since the tech press seems to report on Apple's patents more than just about anybody) where they have patented a lot of things they haven't done (and one can conclude will never do in some cases, based on what they ended up doing instead)

It's guesses in all cases since we are never privy to all the details. But regarding Zen 3 and RDNA2 the guesses based on patents were at least informed with some hits, while the others were free-for-all without any satisfying resolution (e.g. SMT4 *coughs*).

 

[maddie]

ASML's inability to scale with demand has been a disaster for EUV for advanced manufacturing nodes. The reduced mask count helps, but these machines are still slower than the DUV steps.
IIRC, TSMC's N5 isn't 100% EUV (and doesn't need to be anyway). Fab 18 would have a much higher capacity (wpm) if more EUV machines were available.

Have often wondered about that. Anyone know why ASML is so slow to ramp production? This has been a longtime problem with a 5+ year and growing backlog.

 

[Kocicak]

These things are not tennis shoes. These are extremelly complicated machines using proprietary difficult to make parts, with some parts probably made by a single supplier, who is not going to share their knowhow with anybody else and they simply supply what they can produce.

These machines are on the edge of technology and science.

BTW not everything REALLY NEEDS to be made on the latest technology.

 

[soresu]

Have often wondered about that. Anyone know why ASML is so slow to ramp production? This has been a longtime problem with a 5+ year and growing backlog.

EUV is an extremely difficult technology to work with by the sounds of it and took a very long time just to get to this point - perhaps part of why Intel 10nm efforts facepalmed for so long.

Conventional theory is that once a technology is cracked you then work on mass manufacturing it before finally commercialising it.

However in this case I think that they have been chasing the bleeding edge of technical viability for years in the desperate hope of getting there before someone gets the bright idea of doing a complete end to end process change which would make their years (and many $billions) of EUV R&D worthless, which would obviously be a disaster for their bottom line.

I think that they went ahead on EUV lithography machines the moment they were technically viable, rather than mass manufacture* viable.

*at least in so much as semicon lithography machinery is ever mass manufactured.

 

[moinmoin]

perhaps part of why Intel 10nm efforts facepalmed for so long.

Intel's 10nm is DUV, 7nm is Intel's first EUV node.

 

[Doug S]

Have often wondered about that. Anyone know why ASML is so slow to ramp production? This has been a longtime problem with a 5+ year and growing backlog.

It doesn't make fiscal sense for ASML to "ramp production" for something which has basically three customers in the whole world none of whom will need even three digit quantities of this equipment for years.

Sure, they'd all like to get EUV machines more quickly, but if you build the capacity to give them what they want quickly, then you have a bunch of capacity sitting idle for months/years until they need more. The device is so specialized and complex it isn't like they can turn around and start making something else with the same production equipment.

Its like making ultra high end supercars like Konigsegg. When they introduce a new model, they might get 50 people (not sure of the exact volume, but they ain't Ferrari or even Lamborghini) who want one. They would all prefer if they got it immediately, but Konigsegg might produce them over a year or two so just about all of them will have to wait to take delivery. If they geared up to produce all 50 in a week they'd have to lay off their employees and pay rent on an empty factory the rest of the time.

 

[maddie]

The problem is that every process node after 7nm or 5nm is going to be affected adversely. It will not matter how fast you can expand your new node fabs by greater investment if ASML cannot supply the EUV equipment.