Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Thibsie]

I would agree. "The Wall" has some great stuff but also some crap. "Wish You Were Here" is pretty great too. I think a lot of people miss out on pre "Dark Side of the Moon" stuff though. Syd had some good ones before he want crazy.

Echos is excellent.
Let There Be More Light, the intro sounds like Doom music lol
Remember a Day, good stuff
Bike is fun
See Emily Play, great stuff.

I'd list a few more but I don't want to go off topic.

Too late. We're already off topic.
I'll agree 100% though...

 

[jamescox]

Having "Navi" alone proves very little, it can also easily be a tiny IGP in the I/O die for feature parity with Intel.
As Raphael is a Vermeer's successor (after Warhol), there is no change in hell that every desktop-CPU will have HBM on board. If there's no HBM, the interposer also seems kinda wasteful. Not saying that it might not have SKUs with it, but I can't imagine using it for every single CPU form a 3300X's successor and up.

It is a possibility that they would make such a device once they move to interposer based chiplets, but I would agree that there may not be that much of a market for essentially a high end APU. I would only expect interposers to be used in Epyc, maybe high end desktop parts, and possibly some niche mobile parts. It would be useful to have at least a small gpu available across the entire lineup. Intel quick sync uses the gpu; AMD can’t offer that currently since most Ryzen desktop parts do not have a gpu.

It may be an IGP in the IO die. Another possibility is that they have a monolithic die with 8 cores and integrated graphics that is used for everything up to 8 core desktop parts. The interposer is then only used for higher core count parts. At 5 nm, core counts may actually be even higher than current parts, so we may be talking interposer only for ThreadRipper level HEDT parts. Once they move to die stacking, it it hard to predict. Some of their patents show memory stacked on top of gpu chiplets. An HBM 2 die stack is around 100 square mm. Such a stack on top of even a 100 square mm 5 nm gpu would be a very powerful device. It would make a great gaming laptop, but wouldn’t necessarily be worthwhile for the general desktop market. There is also a possibility that it is just a tiny GPU chiplet with no HBM. They are almost certainly moving to interposers for EPYC, so it would make sense to use them for some HEDT parts also.

 

[jamescox]

I have no idea where you pull this stuff from.



Nah, one of my friends who's never used drugs and myself can enjoy Pink Floyd. The real question is, what album was the best?

AMD does seem to have a bunch of code names for the cpu die, the IO die, the whole cpu package, etc. I thought I saw a bunch of them listed somewhere but I can’t remember where. It is mostly irrelevant since knowing the code name doesn’t really give us any information.

 

[A///]

AMD has a codename for the IO die? Do they? I'm not mocking you, James, it's just this is the first time I've read that.

 

[xilli_fiberbit]

I haven't noticed in this article : https://www.techpowerup.com/264536/amd-announces-the-cdna-and-cdna2-compute-gpu-architectures but infinity fabric 3.0 in ZEN4 does the same that CXL :

Much like Intel's Compute eXpress Link (CXL) and PCI-Express gen 5.0, Infinity Fabric 3.0 will support shared memory pools between CPUs and GPUs, enabling scalability of the kind required by exascale supercomputers such as the US-DoE's upcoming "El Capitan" and "Frontier." Cache coherent unified memory reduces unnecessary data-transfers between the CPU-attached DRAM memory and the GPU-attached HBM. CPU cores will be able to directly process various serial-compute stages of a GPU compute operation by directly talking to the GPU-attached HBM and not pulling data to its own main memory. This greatly reduces I/O stress.

 

[soresu]

I haven't noticed in this article : https://www.techpowerup.com/264536/amd-announces-the-cdna-and-cdna2-compute-gpu-architectures but infinity fabric 3.0 in ZEN4 does the same that CXL :

Much like Intel's Compute eXpress Link (CXL) and PCI-Express gen 5.0, Infinity Fabric 3.0 will support shared memory pools between CPUs and GPUs, enabling scalability of the kind required by exascale supercomputers such as the US-DoE's upcoming "El Capitan" and "Frontier." Cache coherent unified memory reduces unnecessary data-transfers between the CPU-attached DRAM memory and the GPU-attached HBM. CPU cores will be able to directly process various serial-compute stages of a GPU compute operation by directly talking to the GPU-attached HBM and not pulling data to its own main memory. This greatly reduces I/O stress.

So basically the dream of Fusion/HSA made reality.

It just took a decade, a bunk CPU uArch and a complete division of GPU uArch's for compute and gaming to make it happen.

 

[DrMrLordX]

@xilli_fiberbit

Pretty sure those design goals are part of the CCIX standard. It also seems like they're aping nVidia's UVM model built into NVLink.

 

[DisEnchantment]

With heterogenous computing, chiplets and die stacking either already in place or coming within the next couple of years I have high hopes for FPGAs to be integrated on the system.

One of the reasons Intel is pushing CXL is because of the need to integrate Altera FPGAs properly. Intel is very aggressive on CPU+FPGA integration.
AMD is also part of CXL. There are politics behind CXL but that is not what I want to highlight here.

Exactly what AMD is trying to do!
I did read a lot about of AMD's patents in the area of FPGAs integration with Host CPUs like the sample below.
View attachment 20961

One of the things they are working on is to have an interconnect mechanism to the host and how the host can schedule work. This is quite typical for an FPGA you might say.
However, bring in HSA and coherency, then the programming paradigm changes and the average programmer can extract performance from these specialized HW.
This is happening already as we speak. The race now is about coherency, interconnects and programming model.

In supercomputing nothing is going to come close to these kind of machines with special purpose FPGAs to accelerate specific workloads, even GPUs cannot come close. You can download an accelerator based on what you are doing.

Dan McNamara who joined AMD and working under Norrod was an SVP at Altera.
If AMD can integrate the Infinity Architecture interconnect slave block on the FPGA and and LUTs can be loaded by the host, you can imagine what an impact this can make.

There are bunch of others things like NVDIMM-P, PIMs (Processing in Memory) which are also areas of intense development in server space.

Well it seems the patent trail from AMD is on to something. There has been a lot of patent applications from AMD related to FPGA and AMD's interest in Xilinx could be real.
Then Dan McNamara was brought in, seems like AMD is making big moves in the FPGA area.
Although I was expecting AMD to take on Lattice Semiconductors, instead they are allegedly going for the 800 pound gorilla in the FPGA/CPLD space.


For me AMD with Xilinx brings back very fond memories of my Uni days. My first self built PC was using the Athlon Thunderbird 1400MHz which I needed because the VHDL simulations were very slow (with the Compaq PC I had) when I was working with the Xilinx Spartan FPGA (can't remember which version)

 

[Vattila]

OP Edit: Updated the thread title (from "Ryzen 5000" to "Ryzen 6000").

 

[soresu]

OP Edit: Updated the thread title (from "Ryzen 5000" to "Ryzen 6000").

Depending on what Warhol is (or if it is) of course.

 

[soresu]

Well it seems the patent trail from AMD is on to something. There has been a lot of patent applications from AMD related to FPGA and AMD's interest in Xilinx could be real.
Then Dan McNamara was brought in, seems like AMD is making big moves in the FPGA area.

It would certainly tie in well with AMD getting support for OneAPI through HipSYCL/ROCm.

The whole point with OneAPI for Intel was unifying CPU, GPU, FPGA, AI/ML accelerators etc under one coding roof.

Here's hoping for their sake it doesn't take AMD forever to deliver on the SW implementation then, because Intel will certainly have a humongous head start on the FPGA side unless Xilinx's own software platform can be made to simply take OneAPI code without a giant amount of engineering in the interim.

 

[soresu]

@xilli_fiberbit

Pretty sure those design goals are part of the CCIX standard. It also seems like they're aping nVidia's UVM model built into NVLink.

I'm still rather confused at the giant gamut of interconnect standards that have arisen and how many AMD are involved with.

I suppose it seems fairly likely that with Intel pushing CXL that AMD will support it in their hardware, but I'm still confused about what the exact benefit of it over PCIe5 is.

 

[moinmoin]

I'm still rather confused at the giant gamut of interconnect standards that have arisen and how many AMD are involved with.

I suppose it seems fairly likely that with Intel pushing CXL that AMD will support it in their hardware, but I'm still confused about what the exact benefit of it over PCIe5 is.

CXL (and others) builds on PCIe 5 actually. PCIe ist just the connection, CXL (and others) worries about cache coherence across different devices.

 

[A///]

25% core increase at all levels
SMT4 on TR...

Yeah, I know we give Richie the finger about that but it sort of makes sense for the ultra tier of TR. A 6990X may see a significant core count increase due to the rumored layering technology.

If AMD is pushing Intel to innovate, then Intel can use their leverage in the SW industry to push for better thread utilization. HT gives around 25-30% better performance in theory, the ROI gets worse with more threads, but there isn't anything wrong there... I think.

Maybe for TR Pro only?

 

[DrMrLordX]

I'm still rather confused at the giant gamut of interconnect standards that have arisen and how many AMD are involved with.

It's basically NVLink vs everyone else. Intel is pushing CXL for . . . whatever reason. Maybe it has features that they need/want for OneAPI that they can't convince the CCIX consortium to implement. i don't really know what both CXL and CCIX exist since they appear to have similar goals.

CXL (and others) builds on PCIe 5 actually. PCIe ist just the connection, CXL (and others) worries about cache coherence across different devices.

Yup! That boils it down rather nicely. CCIX actually works over PCIe 4.x as well.

 

[therealmongo]

Upgraded IOD, please this time AMD, us memory overclocking junkies need to get our 1:1 fix

 

[xilli_fiberbit]

I'm still rather confused at the giant gamut of interconnect standards that have arisen and how many AMD are involved with.

I suppose it seems fairly likely that with Intel pushing CXL that AMD will support it in their hardware, but I'm still confused about what the exact benefit of it over PCIe5 is.

AMD has already infinity fabric which does the same that CXL and infinity fabric will be used for cache coherence between CPU and GPU.

 

[DrMrLordX]

AMD has already infinity fabric which does the same that CXL and infinity fabric will be used for cache coherence between CPU and GPU.

The whole point of CCIX is IF through PCIe interface.

 

[LightningZ71]

Essentially, they already have had that. IF as implemented in Zen 1-2 was essentially running over links that were physically indistinguishable from PCIe. Earlier this year, they rebranded IF to Infinity Architecture (see the story on Anand), which allows a more flexible interconnect between any number of CPUs and GPUs to the gang limit over PCIe physical links. IA, CCIX and CXL are essentially data protocol standards for what runs over the actual physical links themselves. With the proper encapsulation, they would probably function over a USB connection, albeit uselessly slow in practice.

 

[soresu]

Upgraded IOD, please this time AMD, us memory overclocking junkies need to get our 1:1 fix

For Genoa it is guaranteed that the IOD will be shrunk.

Based on the roadmap 'leak' showing Rembrandt APU is 6nm I threw my hat in with the next IOD (or IOD's, there are 2 on Zen2 platform) being on that process.

One would hope that this IOD shrink will also extend to the chipset and nix the need for that tiny fan in the X670/770.

 

[therealmongo]

For Genoa it is guaranteed that the IOD will be shrunk.

Based on the roadmap 'leak' showing Rembrandt APU is 6nm I threw my hat in with the next IOD (or IOD's, there are 2 on Zen2 platform) being on that process.

One would hope that this IOD shrink will also extend to the chipset and nix the need for that tiny fan in the X670/770.

Have you seen any information about the socket they are going to use ?

Is there a possibility we see Zen 4 on AM4 and AM5 ?

 

[maddie]

Have you seen any information about the socket they are going to use ?

Is there a possibility we see Zen 4 on AM4 and AM5 ?

A possibility? Ever heard of Quantum Mechanics?

 

[soresu]

Is there a possibility we see Zen 4 on AM4 and AM5 ?

They promised support for AM4 up to 2020 for a reason, so it seems doubtful that this specific named socket will be supported much longer.

It's not impossible that they might entertain an AM4+ that retains DDR4 memory support but supports Zen3 onwards I suppose.

They've created chips that supported dual memory standards before with Phenom II/Deneb, so it isn't a great stretch when as mentioned above DDR5 is not going to be very affordable for quite some time.

Lacking DDR5 they would have to push people to switch by offering other platform improvements, ala USB4, low power MB chipset, possibly integrated 2.5G ethernet as standard which is long overdue and would push it forward in the consumer space.

 

[therealmongo]

A possibility? Ever heard of Quantum Mechanics?

What are you talking about? There is no spoon

 

[therealmongo]

They promised support for AM4 up to 2020 for a reason, so it seems doubtful that this specific named socket will be supported much longer.

It's not impossible that they might entertain an AM4+ that retains DDR4 memory support but supports Zen3 onwards I suppose.

They've created chips that supported dual memory standards before with Phenom II/Deneb, so it isn't a great stretch when as mentioned above DDR5 is not going to be very affordable for quite some time.

Lacking DDR5 they would have to push people to switch by offering other platform improvements, ala USB4, low power MB chipset, possibly integrated 2.5G ethernet as standard which is long overdue and would push it forward in the consumer space.

Its due to the fact that they have done this in the past that I asked this question, as you have kindly explained in your answer.

We are going to have to wait and see, I believe the current AMD (mindset) wont entertain dual socket for Zen4, hopefully we will see some leaks appearing here and there ...