Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[soresu]

Hmmm interesting. Thanks for the tip on the name:

https://www.eetasia.com/news/article/TSMC-Adds-a-N5P-process

So N5P uses the same design rules as 5nm, meaning AMD could go from 7nm+ -> 5nm -> N5P/"5nm+" without skipping a beat. It looks like, in terms of design rules, 6nm is a dead end.

I did a quick once over from the quoted process numbers.

Using the 15% power reduction over N5 - N5P gets just under a 50% power reduction at iso power over N7, and just under a 30% power reduction over N7+.

If AMD skipped N5 to N5P it would make a nice power reduction over 7nm+ Zen3, closely matching the area reduction if I remember correctly.

This seems more likely than N3, or whatever Samsung's 3nm process is called for Zen4.

The lack of AMD identifying their post 7nm+ process is the only thing making me wonder about this mind you, don't quote me on it.

 

[Richie Rich]

Rumor: Zen 4 at 5nm EUV in early 2021. Maybe NostaSeronx was right about TSMC pushing AMD hard to 5nm.

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www.chinatimes.com

 

[DrMrLordX]

Rumor: Zen 4 at 5nm EUV in early 2021. Maybe NostaSeronx was right about TSMC pushing AMD hard to 5nm.

TSMC doesn't have to push. It's the most logical choice for AMD, and that's entirely what I would expect from them.

 

[Richie Rich]

TSMC doesn't have to push. It's the most logical choice for AMD, and that's entirely what I would expect from them.

Yes, this is one reason. However there might be other reasons. We know that TSMC increased investment up +50% what is huge amount of money. If those extra money went into new 5nm process factory lines then it makes sense that TSMC wants to move high margin products (Apple and server AMD chips) to 5nm ASAP. Another reason might be high demand for 7nm DUV lines for mid-margin ARM SoCs.

 

[Kedas]

It looks like more cores for Zen4
I would think 12 per die or maybe 3 dies of 8 with a smaller I/O die on AM5

AMD: Expect More Cores on Next-Gen Mainstream Ryzen CPUs, No Saturation Point As Software Just Has To Catch-Up

In an interview, AMD's CTO, Mark Papermaster, has revealed that we can expect even more cores on next-generation Ryzen & EPYC CPUs.

wccftech.com

 

[uzzi38]

It looks like more cores for Zen4
I would think 12 per die or maybe 3 dies of 8 with a smaller I/O die on AM5

AMD: Expect More Cores on Next-Gen Mainstream Ryzen CPUs, No Saturation Point As Software Just Has To Catch-Up

In an interview, AMD's CTO, Mark Papermaster, has revealed that we can expect even more cores on next-generation Ryzen & EPYC CPUs.

wccftech.com

I doubt we'll see more cores per die. Thermal density's a pain.

Bigger caches though? Now that I can see.

 

[moinmoin]

I doubt we'll see more cores per die. Thermal density's a pain.

I don't think thermal hotspots will prevent more cores. The silicon design will more and more need to be build around such hotspots though.

 

[uzzi38]

I don't think thermal hotspots will prevent more cores. The silicon design will more and more need to be build around such hotspots though.

I'm not saying it will prevent more cores. I'm saying it will prevent more cores per CCD. Big difference.

Plus, with 8 core CCXs coming into play with Zen 3, we probably won't see an increase in that for a little while.

 

[moinmoin]

I'm not saying it will prevent more cores. I'm saying it will prevent more cores per CCD. Big difference.

Plus, with 8 core CCXs coming into play with Zen 3, we probably won't see an increase in that for a little while.

Right, we already see with Threadripper 3 that it doesn't prevent more cores, even allowing comparable boost range as Ryzen chips still.

I was already referring to more cores per CCD (or comparably topology, which may well change again later), we will see that eventually. But I agree that the increase won't happen in Zen 3. The density increase for 5nm in Zen 4 may make it possible though.

 

[uzzi38]

Zen 4 is a tick, increasing the number of cores in a CCX (and CCD on top) would be something you'd do as a tock.

And there's no physical benefit to increasing the number of CCXes in a CCD back to 2 either. Communication is through the I/O die anyway, packing more cores in to create a second CCX per CCD wouldn't do a thing.

Plus, N5 is a small ppwer efficiency improvement but a very sizable density improvement. Thermal density will be a significant issue with Zen 4.

It makes more sense to leverage the die space for extra cache and/or extra cores in seperate CCDs than it does to put them in the same CCD.

 

[moinmoin]

Thermal density is already a problem now, and AMD is already tackling it in several ways. Will it increasingly be a problem with denser nodes? Yes. Is it an unsolvable problem? As Zen 2 has shown, no.

 

[ksec]

And Mark Papermaster's Interview did sort of confirm a few speculation of my previous post.

AMD CTO Mark Papermaster: More Cores Coming in the 'Era of a Slowed Moore's Law'

Get ready for more cores

www.tomshardware.com

AMD will also evolve its Infinity Fabric to keep up with higher-bandwidth interfaces, like DDR5 and PCIe 5.0.

We asked Papermaster if it would make sense to move up to 32 cores for mainstream users:

"I don’t see in the mainstream space any imminent barrier, and here's why: It's just a catch-up time for software to leverage the multi-core approach," Papermaster said. "But we're over that hurdle, now more and more applications can take advantage of multi-core and multi-threading.[...]"

It is a great interview I encourage everyone to read it. ( Especially those who still think SMT4 is a thing... )

There's a TSMC 5nm+?

Hmmm interesting. Thanks for the tip on the name:

https://www.eetasia.com/news/article/TSMC-Adds-a-N5P-process

So N5P uses the same design rules as 5nm, meaning AMD could go from 7nm+ -> 5nm -> N5P/"5nm+" without skipping a beat. It looks like, in terms of design rules, 6nm is a dead end.

6nm isn't a dead end. It is a cost optimise version of 7nm. And just like 12nm it is going to be a very long node. It is going to live on as all 7nm are depreciated.

Zen 3: Yep. Agreed there. Other stuff as well is almost certain, as pretty much every new arch from here on out will likely increase cache sizes (have to to lower thermal density, will be a major problem in the future)

Zen 4: No point in shrinking I/O afaik, but could be wrong there. Definitely not to 6nm though. It'll likely use GF's 12LPP+ instead (or whetever it's called, their 12nm+ that's slated for late 2020). Agreed on the smaller IPC bump and clocks. Power reduction isn't much, but density improvements is the real bonus from 5nm over 7nm.

Zen 5: Doubt cores per die increasing. Like I said before, thermal density is a real issue. This is where the big arch jump will happen again, so big IPC improvement. As for how, heck if I know.

Shrinking I/O is about cost cutting. I doubt the improvement of 12LPP is much on I/O die as compared to their 14nm offering, Hence Why AMD isn't using it on their I/O. The I/O for DDR5, PCI-E 5.0 will need a redesign and it makes sense to design it in previous generation long node. Which is 6nm for TSMC, or if they want capacity may be going to Samsung.

Yes, there is a Wall on Thermal Density, but not at Zen 5, we could even have an Zen 3 with 16 Core die. As a matter of fact I doubt we will hit on that thermal density wall before we hit into other wall. Thermal issues is quite far down the road at the moment.

 

[DisEnchantment]

Zen 4 is a tick, increasing the number of cores in a CCX (and CCD on top) would be something you'd do as a tock.

And there's no physical benefit to increasing the number of CCXes in a CCD back to 2 either. Communication is through the I/O die anyway, packing more cores in to create a second CCX per CCD wouldn't do a thing.

Plus, N5 is a small ppwer efficiency improvement but a very sizable density improvement. Thermal density will be a significant issue with Zen 4.

It makes more sense to leverage the die space for extra cache and/or extra cores in seperate CCDs than it does to put them in the same CCD.

The other interesting thing with Zen4 in my opinion (supposedly the arch being a tick only) is not only the process tech. But packaging like CoWoS with SoIC and WoW as well.
So Zen4 could possibly achieve higher density scaling not only due to the transistor density increase but possibly due to packaging as well.
3D stacking and packaging will happen, just a question of whether it will be on 5nm or 3nm. Most likely 3nm as it aligns with TSMC roadmaps.

Intel is also working on Wafer on Wafer tech as another method to achieve density scaling beside process improvements. Intel aims to get 2X scaling from Wafer to Wafer and Die to Wafer technologies

 

[moinmoin]

3D stacking and packaging will happen, just a question of whether it will be on 5nm or 3nm. Most likely 3nm as it aligns with TSMC roadmaps.

Wouldn't 3nm align with Zen 5 time wise (assuming AMD manages to keep the yearly cadence alive)?

 

[soresu]

Wouldn't 3nm align with Zen 5 time wise (assuming AMD manages to keep the yearly cadence alive)?

According to recent news, TSMC 3nm is projected to be a year earlier than the original estimate which put it in 2023 - so yes it could be possible.

Details are still non existent though, I don't think TSMC is going MBCFET till after 3nm diverging from Samsung, which could make second source supply difficult at best until they align again.

 

[uzzi38]

We'll probably see some very specific chips from the AMD + TSMC combo utilising SoIC before 3nm. Heck maybe, just maybe, before 5nm.

Course, nothing actually retail, you won't be seeing it for regular server stuff for example that soon, but it'll be around.

 

[jpiniero]

Shrinking I/O is about cost cutting. I doubt the improvement of 12LPP is much on I/O die as compared to their 14nm offering, Hence Why AMD isn't using it on their I/O. The I/O for DDR5, PCI-E 5.0 will need a redesign and it makes sense to design it in previous generation long node. Which is 6nm for TSMC, or if they want capacity may be going to Samsung.

You have to consider the WSA factor. Pretty sure there's still a WSA for 14/12 nm. I forget when it ends but they need something there until then.

 

[scannall]

You have to consider the WSA factor. Pretty sure there's still a WSA for 14/12 nm. I forget when it ends but they need something there until then.

I'm pretty sure that 2020 is the last full year of the WSA. Its winding down finally.

 

[Hitman928]

I'm pretty sure that 2020 is the last full year of the WSA. Its winding down finally.

2021

 

[NostaSeronx]

You have to consider the WSA factor. Pretty sure there's still a WSA for 14/12 nm. I forget when it ends but they need something there until then.

It ends March 1, 2024. With purchasing agreements and arrangements made up to 2022.

FinFETs are not part of AMD's WSA obligation.

 

[soresu]

It ends March 1, 2024. With purchasing agreements and arrangements made up to 2022.

FinFETs are not part of AMD's WSA obligation.

Jeez, this whole WSA thing is like indentured servitude.

One would hope there are at least provisions in the agreement in case GF's non competitive product is hurting AMD's bottom line, or preventing them from designing products to the available processes rather than stooping to fulfill obligations like this.

You have to wonder what was in it for AMD in the first place, because from an outsiders perspective it seems to be a toxic relationship now, given GF seem to have given up on cutting edge process tech.

 

[DrMrLordX]

You have to wonder what was in it for AMD in the first place,

Ask Hector.

 

[Tuna-Fish]

You have to wonder what was in it for AMD in the first place

Survival.

Running fabs is ridiculously expensive, especially when you need to spend several billion every two years or so to upgrade. AMD was already heavily in debt from upgrading them the last time, and then Opteron revenue crashed and it looked like the options were bankruptcy and selling the fabs. The only interested buyer they could found was ATIC, but they wanted assurances that they will have customers in the future. Hence, the WSA.

 

[moinmoin]

You have to consider the WSA factor. Pretty sure there's still a WSA for 14/12 nm. I forget when it ends but they need something there until then.

I'm pretty sure that 2020 is the last full year of the WSA. Its winding down finally.

AMD already has existing 10 years commitments for all their embedded products. That should cover all their relic WSA that may still exist at that point in time. And right now the demand for Zen 2 chips including both IOD and chipset dies coming from GF likely is far above what the WSA would require. The whole WSA very likely is a huge non-issue at this point.

 

[jpiniero]

What I mean is that the IO/Chipet die needs to stay at GloFo for awhile.